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| 型號： | IBM25EMPPC740EBUF2000 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 26/43頁 |
| 文件大?。?/td> | 431K |
| 代理商： | IBM25EMPPC740EBUF2000 |
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Preliminary and subject to change without notice
PPC740 and PPC750 Hardware Specifications
32 of 43
“Clock AC Specications“ for valid SYSCLK and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is dis-
abled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specications given in the document do not apply in PLL-bypass mode.
4. In Clock - off mode, no clocking occurs inside the PPC740 or PPC750 regardless of the SYSCLK input.
5. This limit is 83.3 MHz as specied in Section 3.1.2.1, “Clock AC Specications“.
Table 17 provides sample core-to-L2 frequencies.
Note:
1. Although the PPC750 is designed for L2 bus ratios of 1:1, 1.5:1, 2:1, 2.5:1 and 3:1, this specication
supports the L2 frequency range specied in Section 3.1.2.4, “L2 Clock AC Specications“. For higher
L2 frequencies not supported in this document, please contact your IBM marketing representative.
7.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the PPC740 and PPC750 to pro-
vide power to the clock generation phase-locked loop and L2 cache delay-locked loop
respectively. To ensure stability of the internal clock, the power supplied to the AVdd
input signal should be ltered using a circuit similar to the one shown in Figure 17 .
The circuit should be placed as close as possible to the AVdd pin to ensure it lters out
as much noise as possible. An identical but separate circuit should be placed as close
as possible to the L2AVdd pin.
Figure 17. PLL Power Supply Filter Circuit
7.3 Decoupling Recommendations
Due to the PPC740’s and PPC750’s dynamic power management feature, large address
and data buses, and high operating frequencies, the PPC740 and PPC750 can generate
transient power surges and high frequency noise in its power supply, especially while
driving large capacitive loads. This noise must be prevented from reaching other com-
Table 17. Sample Core-to-L2 Frequencies1
Core
Frequency
in MHz
÷1
÷1.5
÷2
÷2.5
÷3
200
—
133.3
100
80
—
225
—
112.5
90
—
233
—
116.5
93.2
—
250
—
125
100
83.3
266
—
133
106.4
88.6
VDD
AVDD (or L2AVdd)
10
10
F
0.1
F
GND
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