參數(shù)資料
型號(hào)： IBM25403GCX-3JC76C2
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC PROCESSOR, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 31/54頁(yè)
文件大?。?/td> 541K
代理商： IBM25403GCX-3JC76C2
IBM PowerPC 403GCX
37
SRAM, ROM, or I/O Read Request, Wait Extended with Ready
Bank Register Bit Settings
Notes:
1. WBE2:3 are address bits 30:31 if the bus width is programmed as byte or halfword.
2. See Table 20 on page 34 for WBE signal denitions based on bus width.
3. WBE signals can be read/write byte enables based on the setting of IOCR[BEM]. See waveform and note 3 on
4. When in Byte Enable Mode IOCR[BEM] = 1, the BLast signal appears on the multiplexed OE[XSize1][BLast] out-
put, as described in Table 4 on page 8.
5. Wait must be programmed to a value
≥ (CSon + OEon). If Wait > (CSon + OEon), then all signals will retain the
values shown in cycle 4 until the Wait timer expires.
6. If Hold is programmed > 001, all output signals retain the values shown in cycle 7 until the Hold timer expires.
7. If Wait = 00 0000, the Ready input is ignored and single-cycle transfers occur. If Wait > 00 0000, Ready is sampled
starting after the Wait cycles have expired.
8. IOCR[SOR] = 0.
SLF
Burst
Mode
Bus Width
Ready
Enable
Wait
States
CSon
OEon
WEon
WEoff
Hold
Bit 13
Bit 14
Bits 15:16
Bit 17
Bits 18:23
Bit 24
Bit 25
Bit 26
Bit 27
Bits 28:30
0 or 1
0
xx
1
00 0010
0 or 1
x
001
A6:29,1
WBE2[A30],
WBE3[A31]
R/W
CSx5
OE4,5
WBE0:32,3
D0:31
Address Valid
Data In
CSon=0
CSon=1
CSon=0
OEon=0
CSon=0,1
OEon=1,0
CSon=1
OEon=1
Ready7
Wait
Not
Ready
Not
Ready
Sample Ready
Sample Data
Ready
Hold
SysClk
1
2
3
4
5
6
7
8
BusError
Error?
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