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| 型號(hào)： | IBM25403GCX-3JC76C2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 28/54頁 |
| 文件大?。?/td> | 541K |
| 代理商： | IBM25403GCX-3JC76C2 |
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IBM PowerPC 403GCX
34
Address Bus Multiplexing
To support DRAM memories with differing congurations and bus widths, the 403GCX provides an inter-
nally multiplexed address bus controlled by the BIU. Table 21 shows the multiplexed address outputs ref-
erenced by waveforms later in this section.
When the 403GCX is bus master and there are no bus operations in progress, the states of the address
bus outputs are determined by the setting of IOCR[ATC]. If this bit is set to zero, the address bus will be
placed in high impedance. If this bit is set to one, the last address held in the BIU address register will be
driven out on the address bus until bus operations resume.
Table 20. Write Byte Enable Encoding
8-Bit Bus
Width
Transfer Size
Address
WBE0 = WE
WBE1 = 1
WBE2 = A30
WBE3 = A31
Byte
0
0100
Byte
1
0101
Byte
2
0110
Byte
3
0111
16-Bit Bus
Width
Transfer Size
Address
WBE0 = BHE
WBE1 = BLE
WBE2 = A30
WBE3 =A31
Half-word
0
0000
Half-word
2
0010
Byte
0
0100
Byte
1
1001
Byte
2
0110
Byte
3
1011
32-Bit Bus
Width
Transfer Size
Address
WBE0
WBE1
WBE2
WBE3
Word
0
0000
Half-word
0
0011
Half-word
2
1100
Byte
0
0111
Byte
1
1011
Byte
2
1101
Byte
3
1110
Table 21. Multiplexed Address Outputs
Address
Pins
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29
Addr Bits Out
in RAS Cycle
a6
a7
a8
a9
a10 a11 a12 a13 a12 a13 a14 a15 a16 a17 a18 a19 a20 a21 a22
Addr Bits Out
in CAS Cycle
xx
a6
a7
a8
a9
a10 a11 a12 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31
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