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參數(shù)資料
| 型號(hào)： | IBM13T2649NC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 SDRAM SO DIMM(2M x 64小外形雙列直插同步動(dòng)態(tài)RAM模塊) |
| 中文描述： | 200萬(wàn)蘇× 64 SDRAM的內(nèi)存（2米× 64小外形雙列直插同步動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | IBM13T2649NC |
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IBM13T2649NC
2M x 64 SDRAM SO DIMM
88H4961
GA14-4477-01
Rev 3/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 15
Operating Currents
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
Symbol
Parameter
Test Condition
CAS
Latency
t
RC
(min)
Speed
Sort
Organization
x64
480
540
700
440
600
700
400
560
680
380
540
680
Units
Notes
I
CC5
Operating Current
Burst Length = 1
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
CL=1
CL=2
CL=3
90 ns
75 ns
80 ns
120 ns
90 ns
90 ns
180 ns
120 ns
110 ns
300 ns
180 ns
150 ns
t
RC
=
∞
t
CK
=30 ns
t
RC
=
∞
t
CK
=15 ns
t
RC
=
∞
t
CK
=10 ns
t
RC
=
∞
t
CK
=30 ns
t
RC
=
∞
t
CK
=15 ns
t
RC
=
∞
t
CK
=10 ns
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
-10
mA
1, 2, 4
I
CC6
Operating Current
Burst Length = 2
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
mA
1, 2, 3,
4
I
CC7
Operating Current
Burst Length = 4
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
mA
1, 2, 3,
4
I
CC8
Operating Current
Burst Length = 8
t
RC
=
t
RC
(min)
t
CK
≥
t
(min)
I
O
= 0mA
mA
1, 2, 3,
4
I
CC9
Operating Current
Burst Length = Full Page
t
RC
=
Infinity
t
CK
≥
t
(min)
I
O
= 0mA
CL=1
-10
340
mA
1, 2, 3,
4
CL=2
-10
480
CL=3
-10
660
I
CC10
Operating Current
1N Rule
(Continuous Read/Write cycles
with new column address regis-
tered each clock cycle)
t
RC
=
Infinity
t
CK
≥
t
(min)
I
O
= 0mA
CL=1
-10
480
mA
1, 2, 4
CL=2
-10
680
CL=3
-10
880
I
CCA
Serial PD Device Active Power
Supply Current
SCL Clock Frequency = 100kHz
1.0
mA
5
1. The specified values are obtained with the output open.
2. The specified values are valid when addresses and DQ’s are changed no more than once during t
CK
(min).
3. The specified values are obtained when the programmed burst length is executed to completion without interruption by a subse-
quent burst Read or Write cycle.
4. The specified values are for one SO DIMM bank in Operating Mode and the other SO DIMM bank in Active Standby (I
DD2
N).
5. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, input rise and fall times 10ns, input and output timing levels V
DD
x 0.5, output load 1 TTL
gate and CL = 100pf.
Discontinued (12/98 - last order; 9/99 last ship)
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