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參數(shù)資料
| 型號： | IBM13T2649NC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 SDRAM SO DIMM(2M x 64小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 200萬蘇× 64 SDRAM的內(nèi)存（2米× 64小外形雙列直插同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 303K |
| 代理商： | IBM13T2649NC |
IBM13T2649NC
2M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 15
88H4961
GA14-4477-01
Rev 3/98
Functional Description and Timing Diagrams
Refer to the IBM 16Mb Synchronous DRAM data sheet, document GA15-5285-05 (Revised 3/98), for the
functional description and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes: Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
Write Cycle
Symbol
Parameter
-10
Units
Min.
Max.
t
DS
Data In Set-up Time
3
—
ns
t
DH
Data In Hold Time
1
—
ns
t
DPL
Data input to Precharge
10
—
ns
t
DQW
DQM Write Mask Latency
0
—
CLK
Clock Frequency and Latency
Symbol
Parameter
Speed Sort
Units
-10
f
CK
Clock Frequency
100
66
33
MHz
t
CK
Clock Cycle Time
10
15
30
ns
t
AA
CAS Latency
3
2
1
CLK
t
RCD
RAS to CAS Delay
3
2
1
CLK
t
RL
RAS Latency
6
4
2
CLK
t
RC
Bank Cycle Time
9
6
3
CLK
t
RAS
Minimum Bank Active Time
6
4
2
CLK
t
RP
Precharge Time
3
2
1
CLK
t
DPL
Data In to Precharge
1
1
1
CLK
t
DAL
Data In to Active/Refresh
4
3
2
CLK
t
RRD
Bank to Bank Delay Time
2
2
1
CLK
t
CCD
CAS to CAS Delay Time
1
1
1
CLK
t
WL
Write Latency
0
0
0
CLK
t
DQW
DQM Write Mask Latency
0
0
0
CLK
t
DQZ
DQM Data Disable Latency
2
2
2
CLK
t
CSL
Clock Suspend Latency
1
1
1
CLK
Discontinued (12/98 - last order; 9/99 last ship)
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