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參數(shù)資料
| 型號： | IBM13T2649NC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 SDRAM SO DIMM(2M x 64小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 200萬蘇× 64 SDRAM的內存（2米× 64小外形雙列直插同步動態(tài)內存模塊） |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 303K |
| 代理商： | IBM13T2649NC |
IBM13T2649NC
2M x 64 SDRAM SO DIMM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 15
88H4961
GA14-4477-01
Rev 3/98
AC Characteristics
(T
A
= 0 to +70C, V
DD
= 3.3V
±
0.3V)
1. An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must be given followed by a minimum of
two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. AC timing tests have V
IL
= 0.8V and V
IH
= 2.0V with the timing referenced to the 1.40V crossover point.
3. The Transition time is measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
4. AC measurements assume t
T
=1ns.
5. In addition to meeting the transition rate specification, the clock and CKEn must transit between V
IH
and V
IL
(or between V
IL
and
V
IH
) in a monotonic manner.
Clock and Clock Enable Parameters
Symbol
Parameter
-10
Units
Notes
Min.
Max.
t
CK3
Clock Cycle Time, CAS Latency = 3
10
100MHz
ns
t
CK2
Clock Cycle Time, CAS Latency = 2
15
66MHz
ns
t
CK1
Clock Cycle Time, CAS Latency = 1
30
33MHz
ns
t
AC3
Clock Access Time, CAS Latency = 3
—
8
ns
1, 2
t
AC2
Clock Access Time, CAS Latency = 2
—
9
ns
1, 2
t
AC1
Clock Access Time, CAS Latency = 1
—
27
ns
1, 2
t
CKH
Clock High Pulse Width
3.5
—
ns
3
t
CKL
Clock Low Pulse Width
3.5
—
ns
3
t
CES
Clock Enable Set-up Time
3
—
ns
t
CEH
Clock Enable Hold Time
1
—
ns
t
CESP
CKE Set-up Time (Power down mode)
3
—
ns
t
T
Transition Time (Rise and Fall)
1
30
ns
1. Access time is measured at 1.4V. See AC output load circuit.
2. Access time is measured assuming a clock rise time of 1ns. If clock rise time is longer than 1ns, then (trise/2-0.5)ns should be
added to the parameter.
3. Assumes clock rise and fall times are equal to 1ns. If rise or fall time exceeds 1ns, then other AC parameters under consideration
should be compensated by an additional [(trise+tfall)/2-1]ns.
Output
Input
Clock
t
OH
t
SETUP
t
HOLD
t
AC
t
LZ
1.4V
0.8V
1.4V
1.4V
2.0V
t
T
Vtt=1.4V
Output
50
50pF
Z
o
= 50
AC Output Load Circuit
Discontinued (12/98 - last order; 9/99 last ship)
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