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參數(shù)資料
| 型號： | IBM13Q8734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(8M x 72 200腳寄存同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72注冊內(nèi)存模塊（8米× 72 200腳寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 243K |
| 代理商： | IBM13Q8734HCA |
IBM13Q8734HCA
8M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 14
04K8916.C75645C
4/99
Clock and Clock Enable Parameters
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
CK2
Clock Cycle Time
15
66MHz
ns
t
AC2
Clock Access Time
—
11.3
ns
1, 2
t
CH
Clock High Pulse Width
6.0
—
ns
t
CL
Clock Low Pulse Width
6.0
—
ns
t
CKS
Clock Enable Setup Time
2.3
—
ns
t
CKH
Clock Enable Hold Time
1.3
—
ns
t
CKSP
CKE0 Setup Time (Power down mode)
2.3
—
ns
t
T
Transition Time (Rise and Fall)
1.4
10
ns
t
STAB
PLL Stabilization Time
50
—
μ
s
1. CAS latency defined at SDRAMs; DIMM actually has CAS latency of 3.
2. 50pF Load.
Common Parameters
Symbol
Parameter
Value
Units
Min.
Max.
t
S0
Command Setup Time
2.3
—
ns
t
CH
Command Hold Time
1.3
—
ns
t
AS
Address and Bank Select Setup Time
2.3
—
ns
t
AH
Address and Bank Select Hold Time
1.3
—
ns
t
RCD
RAS to CAS Delay
30
—
ns
t
RC
Bank Cycle Time
90
—
ns
t
RAS
Active Command Period
60
100000
ns
t
RP
Precharge Time
30
—
ns
t
RRD
Bank to Bank Delay Time
20
—
ns
t
CCD
CAS to CAS Delay Time
1
—
CLK
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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