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| 型號： | IBM13Q8734HCA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(8M x 72 200腳寄存同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 72注冊內(nèi)存模塊（8米× 72 200腳寄存同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 5/14頁 |
| 文件大?。?/td> | 243K |
| 代理商： | IBM13Q8734HCA |
IBM13Q8734HCA
8M x 72 Registered SDRAM Module
04K8916.C75645C
4/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 14
Output Characteristics
(T
A
= 0 to +70
°
C, V
DD
= 3.3V to 3.6V)
Symbol
Parameter
Min.
Max.
Units
I
I(L)
Input Leakage Current, any input
(0.0V
≤
V
IN
≤
3.6V), All Other Pins Not Under Test = 0V
-20
+20
μ
A
I
O(L)
Output Leakage Current (DQ)
(D
OUT
is disabled, 0.0V
≤
V
OUT
≤
3.6V)
-2
+2
μ
A
V
OH
Output Level (TTL)
Output “H” Level Voltage (I
OUT
= -2.0mA)
2.4
V
DD
V
V
OL
Output Level (TTL)
Output “L” Level Voltage (I
OUT
= +2.0mA)
0.0
0.4
V
I
O(L)
Output Leakage Current (PD1 - PD8)
-10
+10
μ
A
Operating, Standby, and Refresh Currents
(T
A
= 0 to +70
°
C, V
DD
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Value
Units
Notes
Operating Current
t
RC
=
t
RC
(min), t
CK
= min
Active-Precharge command cycling without Burst operation
I
CC1
1 Bank operation
707
mA
1, 2
Precharge Standby Current in Power Down Mode
I
CC2P
CKE0
≤
V
IL
(max), t
CK
= min,
S0, S2 =V
IH
(min)
221
mA
I
CC2PS
CKE0
≤
V
IL
(max), t
CK
= Infinity,
S0, S2 =V
IH
(min)
34
mA
Precharge Standby Current in Non-Power Down Mode
I
CC2N
CKE0
≥
V
IH
(min), t
CK
= min,
S0, S2 =V
IH
(min)
437
mA
3
I
CC2NS
CKE0
≥
V
IH
(min), t
CK
= Infinity,
S0, S2 =V
IH
(min)
70
mA
4
No Operating Current (Active state: 4 bank)
I
CC3N
CKE0
≥
V
IH
(min), t
CK
= min,
S0, S2 =V
IH
(min)
482
mA
3
I
CC3P
CKE0
≤
V
IL
(max), t
CK
= min,
S0, S2 =V
IH
(min)
(Power Down Mode)
275
mA
5
Burst Operating Current
I
CC4
t
CK
= min,
Read/write command cycling,
multiple banks active,
gapless data, BL = 4
1022
mA
2, 6
Auto (CBR) Refresh Current
I
CC5
t
CK
= min, t
RC
= t
RC
(min),
CBR command cycling
1202
mA
Self Refresh Current
I
CC6
CKE0
≤
0.2V
34
mA
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
. Input
signals are changed up to three times during t
RC
(min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during t
ck(min)
.
Discontinued (4/1/00 - last order; 7/31/00 - last ship)
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