參數(shù)資料
型號(hào)： IBM13N16734HC
廠商： IBM Microeletronics
英文描述： 16M x 72 2 Bank Unbuffered SDRAM Module(16M x 72 2組不帶緩沖同步動(dòng)態(tài)RAM模塊)
中文描述： 16米x 72 2行無(wú)緩沖內(nèi)存模組（16米x 72 2組不帶緩沖同步動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 15/18頁(yè)
文件大小： 651K
代理商： IBM13N16734HC
IBM13N16644HC
IBM13N16734HC
16M x 64/72 2 Bank Unbuffered SDRAM Module
19L7123.E93760A
2/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 18
Functional Description and Timing Diagrams
Refer to the IBM 64Mb Synchronous DRAM data sheet, document 19L3264.E35855 (Revised 6/98), for the
functional description and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMsand SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHz
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
μ
s
t
HD:STA
Start Condition Hold Time
4.0
μ
s
t
LOW
Clock Low Period
4.7
μ
s
t
HIGH
Clock High Period
4.0
μ
s
t
SU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
μ
s
t
HD:DAT
Data in Hold Time
0
μ
s
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The Write cycle time (t
WR
) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle.
During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (8/99 - last order; 12/99 - last ship)
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