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參數資料
| 型號： | IBM11M2645L |
| 廠商： | IBM Microeletronics |
| 英文描述： | 2M x 64 DRAM Module(2M x 64 動態(tài)RAM模塊) |
| 中文描述： | 200萬× 64內存（2米× 64動態(tài)內存模塊） |
| 文件頁數： | 1/29頁 |
| 文件大?。?/td> | 548K |
| 代理商： | IBM11M2645L |
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IBM11M2645L
2M x 64 DRAM MODULE
75H5183
GA14-4622-00
Revised 8/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 29
Features
168 Pin JEDEC Standard, 8 Byte Dual In-line
Memory Module
2Mx64 Dual Bank Extended Data Out Page
Mode DIMM
Performance:
All inputs and outputs are TTL (5.0V) compatible
Single 5.0V
±
0.5V Power Supply
Au contacts
Optimized for byte-write non-parity applications
Description
System Performance Benefits:
-Buffered inputs (except RAS, Data)
-Reduced noise (32 V
SS
/V
CC
pins)
-4 Byte Interleave enabled
-Byte write, byte read accesses
-Buffered PDs
Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
Refresh Modes: RAS-Only, CBR and Hidden
Refresh
1024 refresh cycles distributed across 16ms
10/10 addressing (Row/Column)
Card size: 5.25" x 1.0" x 0.354"
DRAMS in SOJ Package
IBM11M2645L is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) which is
organized as a 2Mx64 high speed memory array
designed with EDO DRAMs for non-parity applica-
tions and is configured as 2 1Mx64 banks. The
DIMM uses 8 1Mx16 EDO DRAMs in SOJ pack-
ages. The use of EDO DRAMs allows for a reduc-
tion in Page Mode Cycle time from 40ns (Fast Page)
to 25ns for 60ns DRAM modules.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and
RAS
signals are not
buffered, which preserves the DRAM access specifi-
cations of 60ns and 70ns.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, if a x64 par-
ity DIMM were inserted into a bank of x72 parity
DIMMs, ID0 (grounded) would indicate that at least
one DIMM in that memory bank is x64, and if the
memory controller is designed to do so, all DIMMs in
that memory bank will function as x64s.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x72 parity (5V)
and ECC DIMMs (5V and 3.3V).
-60
-70
t
RAC
RAS Access Time
60ns
70ns
t
CAC
CAS Access Time
20ns
25ns
t
AA
Access Time From Address
35ns
40ns
t
RC
Cycle Time
104ns
124ns
t
HPC
EDO Mode Cycle Time
25ns
30ns
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
IBM11M4730C4M x 72 E12/10, 5.0V, Au.
Discontinued (9/98 - last order; 3/99 last ship)
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