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參數(shù)資料
| 型號： | IBM11M32735BBC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 32M x 72 Stacked DRAM Module(32M x 72 堆棧式動態(tài)RAM模塊) |
| 中文描述： | 32M × 72配置堆疊DRAM模塊（32M × 72配置堆棧式動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 534K |
| 代理商： | IBM11M32735BBC |
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IBM11M32735BBC
32M x 72 Stacked DRAM Module
19L7147.E93788
Released 5/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 29
Features
168-Pin JEDEC-Standard 8-Byte Dual In-Line
Memory Module
32Mx72 (Dual Bank) Extended Data Out Mode
DIMM
Performance:
All inputs and outputs are LVTTL compatible
Single 3.3V,
±
0.3V Power Supply
Gold contacts
Optimized for ECC applications
System Performance Benefits:
- Buffered inputs (except RAS, Data)
- Reduced noise (32 V
SS
/V
CC
pins)
- 4 Byte Interleave enabled
- Buffered PDs
Extended Data Out (EDO) Mode, Read-Modify-
Write Cycles
Refresh Modes: RAS-Only, CBR and Hidden
Refresh
CAS before RAS Refresh / RAS only Refresh -
4096 cycles
12/12 addressing (Row/Column)
Card size: 5.25" x 1.25" x 0.300"
DRAMs in stacked TSOJ Package
Description
IBM11M32735B/C is an industry standard 168-pin
8-byte Dual In-line Memory Module (DIMM) for ECC
applications which is organized as a 32Mx72 high
speed memory array and is configured as 2 16Mx72
banks. The DIMM uses 36 16Mx4 EDO DRAMs in
18 stacked 32M x4 TSOJ packages. The use of
EDO DRAMs allows for a reduction in Page Mode
Cycle time from 40ns (Fast Page) to 20ns for 50ns
DRAM modules.
Improved system performance is provided by the
on-DIMM buffering of selected input signals. The
specified timings include all buffer, net and skew
delays, which simplifies the memory subsystem
design analysis. The data and
RAS
signals are not
buffered, which preserves the DRAM access specifi-
cations of 50 & 60ns.
Presence Detect (PD) and Identification Detect (ID)
bits provide information about the DIMM density,
addressing, performance and features. PD bits can
be dotted at the system level and activated for each
DIMM position using the PD enable (PDE) signal. ID
bits also allow detection of card features, and may
be dot-or’d at the system level to provide information
for the entire DIMM bank. For example, the system
will determine that ECC DIMMs are installed if PD8
is low (0). ID0 need not be sensed since both x72
and x80 ECC DIMMs will function in a x72 bank.
All IBM 168-pin DIMMs provide a high performance,
flexible 8-byte interface in a 5.25” long space-saving
footprint. Related products are the x64 non-parity
(5V and 3.3V) DIMMs and ECC DIMMs (5V and
3.3V).
-50
50ns
18ns
30ns
89ns
20ns
-60
60ns
20ns
35ns
104ns
25ns
t
RAC
t
CAC
t
AA
t
RC
t
HPC
RAS Access Time
CAS Access Time
Access Time From Address
Cycle Time
EDO Mode Cycle Time
Card Outline
1
85
10
94
11
95
40
124
41
125
84
168
(Front)
(Back)
IBM11M16730CB16M x 72 E13/11, 3.3V, Au.
Discontinued (8/98 - last order; 12/98 - last ship)
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