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參數(shù)資料
| 型號： | IBM0418A86SQKA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8 Mb Synchronous Communication SRAM(8M位同步流水線式通訊靜態(tài)RAM) |
| 中文描述： | 8兆同步通信的SRAM（800萬位同步流水線式通訊靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 299K |
| 代理商： | IBM0418A86SQKA |
llwp.03
10/11/2000
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 16
IBM0418A86LQKA
IBM0418A86SQKA
8 Mb Synchronous Communication SRAM
IBM0436A86LQKA
IBM0436A86SQKA
Features
100% bus utilization at high frequencies
Optimized control logic for minimum control
signal interface
CKE to enable or suspend clock operations
Three chip enable pins (CE, CE2, CE2) for
depth expansion with double cycle deselect
Single Read/Write control pin (R/W)
Individual Byte Write controls
Synchronous Pipeline Mode of Operation with
fully coherent Self-Timed Late-Late-Write
Registered control inputs, addresses
and data I/O
Burst feature supports interleaved or linear
burst orders
Sleep mode, for reduced stand-by power
100-pin TQFP package
3.3 V (SQKA) or 2.5 V (LQKA) power supply
and I/O
LVTTL input and output levels
256K x 36 or 512K x 18 organization
Description
The IBM0418A86LQKA/SQKA and
IBM0436A8LQKA/SQKA are 8 Mb Synchronous
Pipeline SRAMs specifically optimized for communi-
cation system applications. These SRAMs utilize the
Late-Late-Write protocol and optimized I/O timing
parameters to permit 100% bus utilization for any
sequence of read and write operations. Please con-
sult application notes for an example at:
http://www.chips.ibm.com/techlib/products/com-
mun/appnotes.html. Developers of non-network sys-
tem communication applications should contact
their local IBM representative for a suitability
assessment and SRAM recommendation.
The clock input (CLK) is used to register all synchro-
nous input pins on its rising edge. Synchronous
inputs include clock enable (CKE), chip enable (CE,
CE2 and CE2), cycle start input (ADV/LD), all
addresses (SA), read/write control (R/W), byte write
controls (BWa, BWb, BWc, BWd) and all data inputs
(DQ).
Asynchronous inputs include output enable (OE),
which may be carefully timed to optimally reduce
bus turn-around time, and Sleep enable (ZZ). The
static burst mode pin (MODE) selects between inter-
leaved and linear burst modes and should be tied
high (or left unconnected) for interleaved burst order
(or if Burst Mode is not used), or tied low for linear
burst order.
Read, Write and Deselect cycles (see
Read/Write
Command Truth Table on page 7) are initiated with
ADV/LD = low. Subsequent Read or Write opera-
tions can load new addresses (ADV/LD = low), or
use the internally generated burst address if
ADV/LD = high (See Burst Sequence Truth Tables
on page 7) based on the initial address that was
loaded.
For write operations, Byte Write inputs (BWa, BWb,
BWc, BWd) are registered each cycle the address is
loaded externally, or advanced from the i burst
counter, data is registered two active cycles later.
Sleep mode is enabled by switching asynchronous
signal ZZ High. When the SRAM is in Sleep mode,
the outputs will go to a High-Z state, and the SRAM
will draw a standby current of I
SB2Z
after a delay of
t
ZZI
. SRAM data will be preserved during Sleep
mode, but any read or write operation that is pend-
ing while entering Sleep mode is not guaranteed. A
recovery time (t
ZZR
) is required before the SRAM
resumes normal operation.
The SRAM operates from a single 3.3 V or 2.5 V
power supply, and supports LVTTL I/O levels.
.
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