- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299188 > HYS72T64300EP-3S-B2 (QIMONDA AG) 64M X 72 DDR DRAM MODULE, DMA240 PDF資料下載
參數(shù)資料
| 型號： | HYS72T64300EP-3S-B2 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁數(shù)： | 34/44頁 |
| 文件大小： | 1430K |
| 代理商： | HYS72T64300EP-3S-B2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
HYS72T[64/128]3x0EP–[25F/3S]–B2
VLP Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.10, 2008-03
4
07302007-3B5G-IYPX
1.2
Description
The Qimonda HYS72T[64/128]3x0EP–[25F/3S]–B2 module
family are Very Low Profile (VLP) Registered DIMM modules
“RDIMMs” with parity bit for address and control bus and
18.30 mm height based on DDR2 technology.
DIMMs are available as ECC modules in 128M
× 72 (1GB),
64M
× 72 (512MB) in organization and density, intended for
mounting into 240-pin connector sockets.
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and are write protected; the second
128 bytes are available to the customer.
TABLE 2
Ordering Information
Min. Row Cycle Time
t
RC
52.5
55
ns
Precharge-All (4 banks) command period
t
PREA
12.5
15
ns
1) Product released after 2007-08-01 will support
t
RAS = 40 ns for all DDR2 speed sort.
2) For products after 2007-08-01.
QAG Speed Code
–25F
–3S
Unit
Note
DRAM Speed Grade
DDR2
–800D
–667D
Module Speed Grade
PC2
–6400D
–5300D
CAS-RCD-RP latencies
5–5–5
t
CK
Product Type1)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
Compliance Code2)
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400P–555–12–T0" where 6400P
means Registered DIMM with Parity bit modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS)
latency =5, Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card "T".
Description
SDRAM Technology
PC2-6400 (5-5-5)
HYS72T128320EP-25F-B2 1GB 2R
×8 PC2–6400P–555–12–T0
2 Ranks, ECC
512Mbit (
×8)
HYS72T128300EP-25F-B2 1GB 1R
×4 PC2–6400P–555–12–U0
1 Rank, ECC
512Mbit (
×4)
HYS72T64300EP-25F-B2
512MB 1R
×8 PC2–6400P–555–12–R0
1 Rank, ECC
512Mbit (
×8)
PC2-5300 (5-5-5)
HYS72T128320EP-3S-B2
1GB 2R
×8 PC2–5300P–555–12–T0
2 Ranks, ECC
512Mbit (
×8)
HYS72T128300EP-3S-B2
1GB 1R
×4 PC2–5300P–555–12–U0
1 Rank, ECC
512Mbit (
×4)
HYS72T64300EP-3S-B2
512MB 1R
×8 PC2–5300P–555–12–R0
1 Rank, ECC
512Mbit (
×8)
相關PDF資料 |
PDF描述 |
|---|---|
| HYS72T64400EFD-3S-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HZ24H2 | 24.15 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ5HC2 | 5.1 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ7HB3 | 7.15 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ7HC1 | 7.4 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T64300HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64300HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
| HYS72T64301HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Registered DDR2 SDRAM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復。