參數(shù)資料
型號(hào)： HYS72T64300EP-3S-B2
廠(chǎng)商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 14/44頁(yè)
文件大?。?/td> 1430K
代理商： HYS72T64300EP-3S-B2
HYS72T[64/128]3x0EP–[25F/3S]–B2
VLP Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.10, 2008-03
21
07302007-3B5G-IYPX
28) 0 °C
≤
T
CASE ≤ 85 °C.
29) 85
°C <
T
CASE ≤ 95 °C.
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x
t
REFI.
31)
t
RPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
t
RPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (
t
RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN = – 72 ps
and
t
JIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+
t
JIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN = – 72 ps
and
t
JIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+
t
JIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
nPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35)
t
WTR is at lease two clocks (2 x tCK) independent of operation frequency.
36) This timing parameter is relaxed than Industry Standard
1)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
6) The output timing reference voltage level is
V
TT.
7) For each of the terms, if not already an integer, round to the next highest integer.
t
CK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
11) MIN (
t
CL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for
t
CL and tCH).
12) The
t
HZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(
t
HZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
14) 0 °C
≤
T
CASE ≤ 85 °C.
15) 85
°C <
T
CASE ≤ 95 °C.
16) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x
t
REFI.
17) The
t
RRD timing parameter depends on the page size of the DRAM organization.
18) The maximum limit for the
t
WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum
t
WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing
t
XARD can be used. In “l(fā)ow active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing
t
XARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the
t
WR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value.
t
DAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
相關(guān)PDF資料
PDF描述
HYS72T64400EFD-3S-B2 64M X 72 DDR DRAM MODULE, DMA240
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