參數(shù)資料
型號(hào)： HYS72T64300EP-3S-B2
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 10/44頁(yè)
文件大小： 1430K
代理商： HYS72T64300EP-3S-B2
HYS72T[64/128]3x0EP–[25F/3S]–B2
VLP Registered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.10, 2008-03
18
07302007-3B5G-IYPX
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ
4) The output timing reference voltage level is
V
TT.
5)
t
RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
6) Products released after 2007-08-01 can support
t
RAS.MIN = 40 ns for all DDR2 speed sort.
7) For products released after 2007-08-01.
3.4
Component AC Timing Parameters
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Parameter
Symbol
DDR2–800
DDR2–667
Unit
Min.
Max.
Min.
Max.
CAS to CAS command delay
t
CCD
2—
2
—
nCK
Average clock high pulse width
t
CH.AVG
0.48
0.52
0.48
0.52
t
CK.AVG
Average clock period
t
CK.AVG
2500
8000
3000
8000
ps
CKE minimum pulse width ( high and
low pulse width)
t
CKE
3—
3
—
nCK
Average clock low pulse width
t
CL.AVG
0.48
0.52
0.48
0.52
t
CK.AVG
Auto-Precharge write recovery +
precharge time
t
DAL
WR +
t
nRP
—WR +
t
nRP
—nCK
Minimum time clocks remain ON after
CKE asynchronously drops LOW
t
DELAY
t
IS + tCK .AVG
+
t
IH
––
t
IS +
t
CK .AVG + tIH
––
ns
DQ and DM input hold time
t
DH.BASE
125
––
175
––
ps
DQ and DM input pulse width for each
input
t
DIPW
0.35
—
0.35
—
t
CK.AVG
DQS input high pulse width
t
DQSH
0.35
—
0.35
—
t
CK.AVG
DQS input low pulse width
t
DQSL
0.35
—
0.35
—
t
CK.AVG
DQS-DQ skew for DQS & associated
DQ signals
t
DQSQ
—
200
—
240
ps
DQS latching rising transition to
associated clock edges
t
DQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
t
CK.AVG
DQ and DM input setup time
t
DS.BASE
50
––
100
––
ps
DQS falling edge hold time from CK
t
DSH
0.2
—
0.2
—
t
CK.AVG
DQS falling edge to CK setup time
t
DSS
0.2
—
0.2
—
t
CK.AVG
CK half pulse width
t
HP
Min(
t
CH.ABS,
t
CL.ABS)
__
Min(
t
CH.ABS,
t
CL.ABS)
__
ps
Data-out high-impedance time from
CK / CK
t
HZ
—
t
AC.MAX
—
t
AC.MAX
ps
Address and control input hold time
t
IH.BASE
250
—
275
—
ps
Control & address input pulse width
for each input
t
IPW
0.6
—
0.6
—
t
CK.AVG
相關(guān)PDF資料
PDF描述
HYS72T64400EFD-3S-B2 64M X 72 DDR DRAM MODULE, DMA240
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