參數(shù)資料
型號: HYS72T256300EP-3.7-C
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: GREEN, RDIMM-240
文件頁數(shù): 6/41頁
文件大?。?/td> 2780K
代理商: HYS72T256300EP-3.7-C
HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
14
07312007-34WH-CYDW
3
Electrical Characteristics
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
V
DD
Voltage on
V
DD pin relative to VSS
–1.0
+2.3
V
1)
1) When
V
DD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
V
DDQ
Voltage on
V
DDQ pin relative to VSS
–0.5
+2.3
V
V
DDL
Voltage on
V
DDL pin relative to VSS
–0.5
+2.3
V
V
IN, VOUT
Voltage on any pin relative to
V
SS
–0.5
+2.3
V
T
STG
Storage Temperature
–55
+100
°C
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Symbol
Parameter
Rating
Unit
Note
Min.
Max.
T
CASE
Operating Temperature
0
95
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85
°C the Auto-Refresh command interval has to be reduced to t
REFI= 3.9 s
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of
I
DD6 by approximately 50%
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