參數(shù)資料
型號: HYS72T256300EP-3.7-C
廠商: QIMONDA AG
元件分類: DRAM
英文描述: 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: GREEN, RDIMM-240
文件頁數(shù): 21/41頁
文件大?。?/td> 2780K
代理商: HYS72T256300EP-3.7-C
HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
28
07312007-34WH-CYDW
TABLE 18
ODT AC Characteristics and Operating Conditions for DDR2-533
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
t
AOND
ODT turn-on delay
2
t
CK
t
AON
ODT turn-on
t
AC.MIN
t
AC.MAX + 1 ns
ns
1)
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from
t
AOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK = 5 ns.
t
AONPD
ODT turn-on (Power-Down Modes)
t
AC.MIN + 2 ns
2
t
CK + tAC.MAX + 1 ns
ns
t
AOFD
ODT turn-off delay
2.5
t
CK
t
AOF
ODT turn-off
t
AC.MIN
t
AC.MAX + 0.6 ns
ns
2)
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from
t
AOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
t
CK = 5 ns.
t
AOFPD
ODT turn-off (Power-Down Modes)
t
AC.MIN + 2 ns
2.5
t
CK + tAC.MAX + 1 ns
ns
t
ANPD
ODT to Power Down Mode Entry Latency
3
t
CK
t
AXPD
ODT Power Down Exit Latency
8
t
CK
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