參數(shù)資料
型號(hào)： HYS72T256300EP-3.7-C
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝： GREEN, RDIMM-240
文件頁(yè)數(shù)： 13/41頁(yè)
文件大小： 2780K
代理商： HYS72T256300EP-3.7-C
HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
20
07312007-34WH-CYDW
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–667
28) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85
°C
and 95
°C.
29) 0 °C
≤ T
CASE ≤ 85 °C
30) 85
°C < T
CASE ≤ 95 °C
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
32)
t
RPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
t
RPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (
t
RPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN = – 72 ps
and
t
JIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+
t
JIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN = – 72 ps
and
t
JIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+
t
JIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
nPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP = 15 ns, the device will support
t
nRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36)
t
WTR is at lease two clocks (2 x tCK) independent of operation frequency.
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
DQ output access time from CK / CK
t
AC
–450
+450
ps
9)
CAS to CAS command delay
t
CCD
2—
nCK
Average clock high pulse width
t
CH.AVG
0.48
0.52
t
CK.AVG
10)11)
Average clock period
t
CK.AVG
3000
8000
ps
CKE minimum pulse width ( high and low pulse
width)
t
CKE
3—
nCK
12)
Average clock low pulse width
t
CL.AVG
0.48
0.52
t
CK.AVG
Auto-Precharge write recovery + precharge time
t
DAL
WR +
t
nRP
—nCK
13)14)
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t
DELAY
t
IS + tCK .AVG +
t
IH
––
ns
DQ and DM input hold time
t
DH.BASE
175
––
ps
DQ and DM input pulse width for each input
t
DIPW
0.35
—
t
CK.AVG
DQS output access time from CK / CK
t
DQSCK
–400
+400
ps
DQS input high pulse width
t
DQSH
0.35
—
t
CK.AVG
DQS input low pulse width
t
DQSL
0.35
—
t
CK.AVG
DQS-DQ skew for DQS & associated DQ signals
t
DQSQ
—240
ps
16)
DQS latching rising transition to associated clock
edges
t
DQSS
– 0.25
+ 0.25
t
CK.AVG
17)
DQ and DM input setup time
t
DS.BASE
100
––
ps
18)19)20)
DQS falling edge hold time from CK
t
DSH
0.2
—
t
CK.AVG
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