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參數(shù)資料
| 型號： | HYS72T256300EP-3.7-C |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| 封裝： | GREEN, RDIMM-240 |
| 文件頁數(shù)： | 10/41頁 |
| 文件大?。?/td> | 2780K |
| 代理商： | HYS72T256300EP-3.7-C |
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HYS72T256300EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
Internet Data Sheet
Rev. 1.0, 2007-07
18
07312007-34WH-CYDW
Control & address input pulse width for each input
t
IPW
0.6
—
t
CK.AVG
Address and control input setup time
t
IS.BASE
175
—
ps
24)25)
DQ low impedance time from CK/CK
t
LZ.DQ
2x
t
AC.MIN
tAC.MAX
ps
DQS/DQS low-impedance time from CK / CK
t
LZ.DQS
t
AC.MIN
t
AC.MAX
ps
MRS command to ODT update delay
t
MOD
012
ns
Mode register set command cycle time
t
MRD
2—
nCK
OCD drive mode output delay
t
OIT
012
ns
DQ/DQS output hold time from DQS
t
QH
t
HP – tQHS
—ps
26)
DQ hold skew factor
t
QHS
—300
ps
27)
Average periodic refresh Interval
t
REFI
—7.8
s
28)29)
—3.9
s
Auto-Refresh to Active/Auto-Refresh command
period
t
RFC
127.5
—
ns
31)
Precharge-All (8 banks) command period
t
RP
t
RP +1 × tCK
—ns
Read preamble
t
RPRE
0.9
1.1
t
CK.AVG
32)33)
Read postamble
t
RPST
0.4
0.6
t
CK.AVG
Active to active command period for 1KB page
size products
t
RRD
7.5
—
ns
Active to active command period for 2KB page
size products
t
RRD
10
—
ns
Internal Read to Precharge command delay
t
RTP
7.5
—
ns
35)
Write preamble
t
WPRE
0.35
—
t
CK.AVG
Write postamble
t
WPST
0.4
0.6
t
CK.AVG
Write recovery time
t
WR
15
—
ns
Internal write to read command delay
t
WTR
7.5
—
ns
Exit power down to read command
t
XARD
2—
nCK
Exit active power-down mode to read command
(slow exit, lower power)
t
XARDS
8 – AL
—
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
t
XP
2—
nCK
Exit self-refresh to a non-read command
t
XSNR
t
RFC +10
—
ns
Exit self-refresh to read command
t
XSRD
200
—
nCK
Write command to DQS associated clock edges
WL
RL – 1
nCK
1) For details and notes see the relevant Qimonda component data sheet
2)
V
DDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until
V
REF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is
V
TT. component datasheet
Parameter
Symbol
DDR2–800
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72T256322HP | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256322HP-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Dual-Die Registered DDR2 SDRAM Modules |
| HYS72T256420HFD-3.7-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
| HYS72T256420HFD-3S-A | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:240-Pin Fully-Buffered DDR2 SDRAM Modules |
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