- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370806 > HYS72D256520GR (INFINEON TECHNOLOGIES AG) 184 Pin Registered Double Data Rate SDRAM Modules PDF資料下載
參數(shù)資料
| 型號： | HYS72D256520GR |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 184 Pin Registered Double Data Rate SDRAM Modules |
| 中文描述： | 184針注冊雙倍數(shù)據(jù)速率SDRAM模塊 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 638K |
| 代理商： | HYS72D256520GR |
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Application Note
Data Sheet
23
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2
signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM
documentation.
b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET
deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the
address signals must maintain valid levels after RESET low has been applied. It is highly recommended that
CKE continue to remain low during this operation.
4. The DIMM is in lowest power Self Refresh mode.
Self Refresh Exit (RESET low, clocks powered off) — Optional
1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL
operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be
affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle.
Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the
DIMM is stable) is 100 microseconds.
2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM
connector). CKE must be maintained low and all other inputs should be driven to a known state. In general
these commands can be determined by the system designer. One option is to apply an SDRAM ‘NOP’
command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence
(ideally this would be a ‘NOP Deselect’ command). A second option is to apply low levels on all of the register
inputs, to be consistent with the state of the register outputs.
3. The system switches RESET to a logic ‘high’ level. The SDRAM is now functional and prepared to receive
commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is
not required (during this period, register inputs must remain stable).
4. The system must maintain stable register inputs until normal register operation is attained. The registers have
an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned
on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It
is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the
DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous
switching of RESET from low to high until the registers are stable and ready to accept an input signal, is
specified in the register and DIMM do-umentation.
5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure.
Self Refresh Entry (RESET low, clocks running) — Optional
Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this
is an alternate operating mode for these DIMMs.
1. System enters Self Refresh entry command. (CKE
→
Low, CS
→
Low, RAS
→
Low, CAS
→
Low, WE
→
High)
Note:The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a
Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input
conditions to the SDRAM are Don’t Cares — with the exception of CKE.
2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state,
independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level
at the DDR SDRAMs.
3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET
deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the
control and the address signals must maintain valid levels after RESET low has been applied. It is highly
recommended that CKE continue to remain low during the operation.
4. The DIMM is in a low power, Self Refresh mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72D32000GR-7-A | Connectors, PCB header and jumpers Multipole |
| HYS72D128020GR-8-A | Cable Termination Tool; For Use With:MediaFlex and Interface Outlets, GigaFlex Modules; Connector Type:Modular RoHS Compliant: NA |
| HYS72D128020GR-8-B | Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:2 RoHS Compliant: Yes |
| HYS72D32000GR-8-A | Connectors, PCB header and jumpers Multipole RoHS Compliant: Yes |
| HYS72D64000GR-8-A | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D256520GR-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYS72D256520GR-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 Pin Registered Double Data Rate SDRAM Modules |
| HYS72D256520GR-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DDR Synchronous DRAM |
| HYS72D256520GR-8-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?2GB (256Mx72) PC1600 2-bank available 3Q02? |
| HYS72D256920HBR-6-C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double-Data-Rate SDRAM Module |
發(fā)布緊急采購，3分鐘左右您將得到回復。