參數(shù)資料
型號(hào): HYS72D256520GR
廠商: INFINEON TECHNOLOGIES AG
英文描述: 184 Pin Registered Double Data Rate SDRAM Modules
中文描述: 184針注冊(cè)雙倍數(shù)據(jù)速率SDRAM模塊
文件頁數(shù): 14/25頁
文件大?。?/td> 638K
代理商: HYS72D256520GR
HYS72D256520GR-7-A
Registered Double Data Rate SDRAM Modules
Electrical Characteristics
Data Sheet
14
Rev. 1.02, 2003-12
10282003-P6EY-RWQ2
Auto-Refresh Current:
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current:
CKE
0.2 V; external clock on;
t
CK
=
t
CKMIN
Operating Current:
four bank; four bank interleaving with BL = 4; Refer to the following page for
detailed test conditions.
I
DD5
I
DD6
I
DD7
Table 9
Product Type & Organisation
I
DD
Specifications
HYS72D256520GR-7-A
2GB
×
72
2 Ranks
7
typ.
4008
4188
736
1816
740
880
2356
4548
3198
6168
466
7248
Unit Note/ Test Conditions
5)
max.
4908
5088
880
2176
1384
1024
2896
5448
5358
7428
556
8688
I
DD0
I
DD1
I
DD2P
I
DD2F
I
DD2Q
I
DD3P
I
DD3N
I
DD4R
I
DD4W
I
DD5
I
DD6
I
DD7
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1)4)
1) The module
I
DD
values are calculated from the component
I
datasheet values are:
n
*
I
DD
×
[component] for single bank modules (n: number of components per module bank)
n
*
I
DD
×
[component] +
n
*
I
DD3N
[component] for two bank modules (n: number of components per module bank)
2) The module
I
DD
values are calculated from the component
I
DD
datasheet values are:
n
*
I
DD
×
[component] for single bank modules (n: number of components per module bank)
2
*
n
*
I
DD
×
[component] for single two bank modules (n: number of components per module bank)
3) DQ I/O (
I
DDQ
) currents are not included into calculations: module
I
DD
values will be measured differently depending on load
conditions
4) DRAM component currents only: module
I
DD
will be measured differently depending upon register and PLL operation
currents
5) Test condition for maximum values:
V
DD
= 2.7 V,
T
A
= 10 °C
1)3)4)
2)4)
2)4)
2)4)
2)4)
2)4)
1)3)4)
1)4)
1)4)
2)4)
1)3)4)
5)
Table 8
Parameter
I
DD
Conditions
Symbol
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