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| 型號： | HYM71V16755HCT8M-P |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HYM71V16755HCT8M-P |
PC100 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01
11
HYM71V16755HCT8M Series
AAC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
If tR & tF > 1ns, then [(tR+tF)/2-1]ns should be added to the parameter
2.Access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v
If tR > 1ns, then (tR/2-0.5)ns should be added to the parameter
Parameter
Symbol
-8
-P
-S
Unit
Note
Min
Max
Min
Max
Min
Max
System Clock
Cycle Time
CAS Latency = 3
tCK3
8
1000
10
1000
10
1000
ns
CAS Latency = 2
tCK2
10
12
ns
Clock High Pulse Width
tCHW
3
-
3
-
3
-
ns
1
Clock Low Pulse Width
tCLW
3
-
3
-
3
-
ns
1
Access Time
From Clock
CAS Latency = 3
tAC3
-
6
-
6
-
6
ns
2
CAS Latency = 2
tAC2
-
6
-
6
-
6
ns
Data-Out Hold Time
tOH
3
-
3
-
3
-
ns
Data-Input Setup Time
tDS
2
-
2
-
2
-
ns
1
Data-Input Hold Time
tDH
1
-
1
-
1
-
ns
1
Address Setup Time
tAS
2
-
2
-
2
-
ns
1
Address Hold Time
tAH
1
-
1
-
1
-
ns
1
CKE Setup Time
tCKS
2
-
2
-
2
-
ns
1
CKE Hold Time
tCKH
1
-
1
-
1
-
ns
1
Command Setup Time
tCS
2
-
2
-
2
-
ns
1
Command Hold Time
tCH
1
-
1
-
1
-
ns
1
CLK to Data Output in Low-Z Time
tOLZ
1
-
1
-
1
-
ns
CLK to Data
Output in High-Z
Time
CAS Latency = 3
tOHZ3
3
6
3
6
3
6
ns
CAS Latency = 2
tOHZ2
3
6
3
6
3
6
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYM71V16C735AT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx72|3.3V|K/H|x9|SDR SDRAM - Registered DIMM 128MB |
| HYM71V16C735AT8-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYM71V16C735AT8-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x72 SDRAM Module |
| HYM71V16C735BT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx72|3.3V|K/H|x8|SDR SDRAM - Registered DIMM 128MB |
| HYM71V16C735HCT8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx72|3.3V|K/H|x9|SDR SDRAM - Registered DIMM 128MB |
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