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參數(shù)資料
| 型號： | HYM71V16755HCT8M-P |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 SYNCHRONOUS DRAM MODULE, 6 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 236K |
| 代理商： | HYM71V16755HCT8M-P |
PC100 SDRAM Unbuffered DIMM
Rev. 0.4/Dec. 01
10
HYM71V16755HCT8M Series
DC CHARACTERISTICS I (TA=0 to 70°C, VDD=3.3±0.3V)
Note :
1.VIN = 0 to 3.6V, All other pins are not tested under VIN =0V
2.DOUT is disabled, VOUT=0 to 3.6
DC CHARACTERISTICS II
Note :
1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open
2. Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HYM71V16755HCT 8M-8/P/S
4.HYM71V16755HCLT8M-8/P/S
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
ILI
-9
9
uA
1
Output Leakage Current
ILO
-1
1
uA
2
Output High Voltage
VOH
2.4
-
V
IOH = -2mA
Output Low Voltage
VOL
-0.4
V
IOL = +2mA
Parameter
Symbol
Test Condition
Speed
Unit
Note
-8
-P
-S
Operating Current
IDD1
Burst length=1, One bank active
tRC
≥ tRC(min), IOL=0mA
990
900
mA
1
Precharge Standby Current
in Power Down Mode
IDD2P
CKE
≤ VIL(max), tCK = 15ns
18
mA
IDD2PS
CKE
≤ VIL(max), tCK =
∞
9
Precharge Standby Current
in Non Power Down Mode
IDD2N
CKE
≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins
≥ VDD-0.2V or ≤ 0.2V
135
mA
IDD2NS
CKE
≥ VIH(min), tCK =
∞
Input signals are stable.
135
Active Standby Current
in Power Down Mode
IDD3P
CKE
≤ VIL(max), tCK = 15ns
45
mA
IDD3PS
CKE
≤ VIL(max), tCK =
∞
45
Active Standby Current
in Non Power Down Mode
IDD3N
CKE
≥ VIH(min), CS ≥ VIH(min), tCK = 15ns
Input signals are changed one time during
30ns. All other pins
≥ VDD-0.2V or ≤ 0.2V
270
mA
IDD3NS
CKE
≥ VIH(min), tCK =
∞
Input signals are stable.
180
Burst Mode Operating
Current
IDD4
tCK
≥ tCK(min), IOL=0mA
All banks active
CL=3
1080
990
mA
1
CL=2
1170
990
Auto Refresh Current
IDD5
tRRC
≥ tRRC(min), All banks active
1800
mA
2
Self Refresh Current
IDD6
CKE
≤ 0.2V
18
mA
3
Burst length=1, One bank active
tRC
≥ tRC(min), IOL=0mA
7.2
mA
4
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