參數(shù)資料
型號(hào)： HYE25L256160AF
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256MBit Mobile-RAM
中文描述： 片256Mbit移動(dòng)- RAM的
文件頁(yè)數(shù)： 4/55頁(yè)
文件大小： 1053K
代理商： HYE25L256160AF
Data Sheet
4
V1.1, 2003-04-16
256-Mbit Mobile-RAM
Mobile-RAM
HYE25L256160AC
1
Overview
1.1
Features
16 Mbits
×
16 organisation
Fully synchronous to positive clock edge
Four internal banks for concurrent operation
Data mask (DM) for byte control with write and read data
Programmable CAS latency: 2 or 3
Programmable burst length: 1, 2, 4, 8, or full page
Programmable wrap sequence: sequential or interleaved
Random column address every clock cycle (1-N rule)
Deep power down mode
Extended mode register for Mobile-RAM features
Temperature compensated self refresh with on-die temperature sensor
Partial array self refresh
Power down and clock suspend mode
Automatic and controlled precharge command
Auto refresh mode (CBR)
8192 refresh cycles / 64 ms
Self-refresh with programmble refresh period
Programmable power reduction feature by partial array activation during self-refresh
V
DDQ
= 1.8V or 2.5 V or 3.3 V
V
DD
= 2.5 V or 3.3 V
P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm
2
)
Operating temperature range: extended (–25 °C to +85 °C)
1.2
Description
The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized as
4 banks x 4 Mbit x 16 with additional features for mobile applications. The synchronous Mobile-RAM achieves
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes
the output data to a system clock.
The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory
array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps
which drastically reduces the self refresh current, depending on the case temperature of the components in the
system application. In addition a “Deep Power Down Mode” is available. Operating the four memory banks in an
Table 1
Part Number Speed Code
max. Clock Frequency
min. Clock Period
min. Access Time from Clock
min. Clock Period
min. Access Time from Clock
Performance
1)
1) for VDDQ = 2.5 V; see
Table 10
for VDDQ dependent performance
–7.5
133
7.5
6.0
9.5
6.0
–8
125
8.0
6.0
9.5
6.0
Unit
MHz
ns
ns
ns
ns
@CL3
@CL3
@CL3
@CL2
@CL2
f
CK3
t
CK3
t
AC3
t
CK2
t
AC2
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