參數(shù)資料
型號: HYE18P32161ACL70
廠商: INFINEON TECHNOLOGIES AG
英文描述: JT 23C 21#20 2#16 SKT PLUG
中文描述: 32M的異步/頁的CellularRAM
文件頁數(shù): 6/33頁
文件大?。?/td> 641K
代理商: HYE18P32161ACL70
HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Data Sheet
6
V2.0, 2003-12-16
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
CellularRAM - Interface Configuration Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standard Ballout - HYE18P32161AC(-/L)70/85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Refresh Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Control Register Write Access Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PASR Programming Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PASR Configuration Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Asynchronous Read - Address Controlled (CS1 = OE =
V
IL
, WE =
V
IH
, UB and/or LB =
V
IL
, ZZ =
V
IH
)
20
Asynchronous Read (WE =
V
IH
, ZZ =
V
IH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Asynchronous Page Read Mode (ZZ =
V
IH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Asynchronous Write - WE Controlled (OE =
V
IH
or
V
IL
, ZZ =
V
IH
). . . . . . . . . . . . . . . . . . . . . . . . . . 23
Asynchronous Write - CS1 Controlled (OE =
V
IH
or
V
IL
, ZZ =
V
IH
) . . . . . . . . . . . . . . . . . . . . . . . . . 23
Asynchronous Write - UB, LB Controlled (OE =
V
IH
or
V
IL
, ZZ =
V
IH
). . . . . . . . . . . . . . . . . . . . . . . 24
Asynchronous Write to Control Register (OE =
V
IH
or
V
IL
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Deep Power Down Entry/ Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
P-VFBGA-48 (Plastic Very Thin Fine Pitch Ball Grid Array Package) . . . . . . . . . . . . . . . . . . . . . . 29
Low Frequency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
S/W Register Entry timing (Address input = 1FFFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RCR Mapping in S/W Register Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
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