參數(shù)資料
型號(hào): HYB39S64160AT-6
廠商: INFINEON TECHNOLOGIES AG
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54
封裝: 10.16 X 22.22 MM, 0.80 MM PITCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù): 8/18頁(yè)
文件大?。?/td> 118K
代理商: HYB39S64160AT-6
INFINEON Technologies
16
HYB39S6416A/BT-5.5/-6/-7
64MBit Synchronous DRAM
Notes for AC Parameters:
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests for LV-TTL versions have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.5 V
crossover point. The transition time is measured between V ih and Vil. All AC measurements assume tT=1ns
with the AC output load circuit shown in fig.1. Specified tac and toh parameters are measured with a 30 pF only,
without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V..
3. If clock rising time is longer than 1 ns, a time (tT/2 - 0.5) ns has to be added to this parameter.
4. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock,
as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole number)
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit
command is registered.
fig.1
50 pF
I/O
Measurement conditions for
tac and toh
SPS03410
Output
V
50
pF
30
50
=
Z
tt
+
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
T
OUTPUT
1.4 V
t
LZ
AC
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
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