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參數(shù)資料
| 型號： | HYB39S64160AT-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5 ns, PDSO54 |
| 封裝： | 10.16 X 22.22 MM, 0.80 MM PITCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 1/18頁 |
| 文件大小： | 118K |
| 代理商： | HYB39S64160AT-6 |
INFINEON Technologies
1
7.99
HYB39S64160A/BT-5.5/-6/-7
64MBit Synchronous DRAM
4M x 16 MBit Synchronous DRAM
for High Speed Graphics Applications
The HYB39S64160A/BT-5.5/-6/-7 are high speed dual bank Synchronous DRAM’s based on
INFINEON 0.25
m (A1-die) and 0.2m (B-die) process and organized as 4 banks x 1Mb x 16.
These synchronous devices achieve high speed data transfer rates up to 183 MHz by employing a
chip architecture that prefetches multiple bits and then synchronizes the output data to a system
clock. The chip is fabricated with INFINEON’ advanced 16MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the two memory banks in an interleaved fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 183
MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V +/- 0.3V power supply and are available in TSOPII packages.
These Synchronous DRAM devices are available with LV-TTL interfaces.
High Performance:
Fully Synchronous to Positive Clock Edge
0 to 70
°C operating temperature
Dual Banks controlled by A11 ( Bank Select)
Programmable CAS Latency : 2, 3
Programmable Wrap Sequence : Sequential
or Interleave
Programmable Burst Length: 1, 2, 4, 8
-5.5
-6
-7
Units
fCKmax @ CL=3
183
166
143
MHz
tCK3
5.5
6
7
ns
tAC3
4.5
5
5.5
ns
fCKmax @ CL=2
133
125
115
MHz
tCK2
7.5
8
9
ns
tAC2
5.4
6
ns
full page(optional) for sequencial wrap
around
Multiple Burst Read with Single Write
Operation
Automatic
and
Controlled
Precharge
Command
Data Mask for Read / Write control
Dual Data Mask for byte control
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
4096 refresh cycles / 64 ms
Latency 2 @ 133 MHz
Latency 3 @ 183 MHz
Random Column Address every CLK
( 1-N Rule)
Single 3.3V +/- 0.3V Power Supply
LVTTL Interface
Plastic Packages:
P-TSOPII-54 400mil width
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB39T256160TT-5 | MEMORY SPECTRUM |
| HYB39T256160TT-6 | MEMORY SPECTRUM |
| HYB39T256160TT-7 | MEMORY SPECTRUM |
| HYB39T256160TT-75 | MEMORY SPECTRUM |
| HYB39T256160TT-7F | MEMORY SPECTRUM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S64160AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S64160AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HYB39S64160AT-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 MBit Synchronous DRAM |
| HYB39S64160AT-8B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:64 MBit Synchronous DRAM |
| HYB39S64160ATL-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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