參數(shù)資料
型號: HYB3117805BSJ-60
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 2M x 8-Bit Dynamic RAM 2k Refresh
中文描述: 2M X 8 EDO DRAM, 60 ns, PDSO28
封裝: 0.400 INCH, PLASTIC, SOJ-28
文件頁數(shù): 5/23頁
文件大?。?/td> 176K
代理商: HYB3117805BSJ-60
HYB 5(3)117805/BSJ-50/-60
2M
×
8 EDO-DRAM
Semiconductor Group
5
1998-10-01
Average
V
CC
supply current
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC MIN.
)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
refresh cycles
I
CC1
80
70
mA
mA
2, 3, )4
2, 3, 4
2
mA
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC MIN.
)
Average
V
CC
supply current, during hyper page
mode (EDO)
I
CC3
80
70
mA
mA
2, 4
2, 4
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
t
PC
=
t
PC MIN.
)
Standby
V
CC
supply current
(RAS = CAS =
V
CC
– 0.2 V)
Average
V
CC
supply current, during CAS-
before-RAS refresh mode
I
CC4
35
30
mA
mA
2, 3, 4
2, 3, 4
I
CC5
1
mA
1
-50 ns version
-60 ns version
(RAS, CAS cycling:
t
RC
=
t
RC MIN.
)
I
CC6
80
70
mA
mA
2, 4
2, 4
Capacitance
T
A
= 0 to 70
°
C,
V
CC
= 5 V
±
10 %,
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A10)
C
I1
C
I2
C
IO
5
pF
Input capacitance (RAS, CAS, WE, OE)
7
pF
I/O capacitance (I/O1 - I/O8)
7
pF
DC Characteristics
(cont’d)
T
A
= 0 to 70
°
C,
V
SS
= 0 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Test
Condition
min.
max.
相關(guān)PDF資料
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