參數(shù)資料
型號: HYB3117405BJ-70
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 3.3V 4M x 4-Bit EDO-Dynamic RAM
中文描述: 4M X 4 EDO DRAM, 70 ns, PDSO24
文件頁數(shù): 8/26頁
文件大?。?/td> 285K
代理商: HYB3117405BJ-70
Semiconductor Group
8
HYB 3116(7)405BJ/BT(L) -50/-60/-70
3.3V 4Mx4-DRAM
AC Characteristics
5)6)
16E
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
t
REF
t
REF
84
104
124
ns
RAS precharge time
30
40
50
ns
RAS pulse width
50
10k
60
10k
70
10k
ns
CAS pulse width
8
10k
10
10k
12
10k
ns
Row address setup time
0
0
0
ns
Row address hold time
8
10
10
ns
Column address setup time
0
0
0
ns
Column address hold time
8
10
12
ns
RAS to CAS delay time
12
37
14
45
14
53
ns
RAS to column address delay
10
25
12
30
12
35
ns
RAS hold time
13
15
17
ns
CAS hold time
40
50
60
ns
CAS to RAS precharge time
5
5
5
ns
Transition time (rise and fall)
1
50
1
50
1
50
ns
7
Refresh period for HYB5116405
64
64
64
ms
Refresh period for HYB5117405
32
32
32
ms
Refresh period for L-version
256
256
256
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
50
60
70
ns
8, 9
Access time from CAS
13
15
17
ns
8, 9
Access time from column address
t
AA
OE access time
25
30
35
ns
8,10
t
OEA
13
15
17
ns
Column address to RAS lead time
t
RAL
Read command setup time
25
30
35
ns
t
RCS
t
RCH
t
RRH
0
0
0
ns
Read command hold time
0
0
0
ns
11
Read command hold time
referenced to RAS
0
0
0
ns
11
CAS to output in low-Z
t
CLZ
0
0
0
ns
8
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