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參數(shù)資料
| 型號： | HYB25D128800AT-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 51/79頁 |
| 文件大?。?/td> | 2596K |
| 代理商： | HYB25D128800AT-6 |
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HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Electrical Characteristics
Data Sheet
51
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
4
Electrical Characteristics
4.1
Operating Conditions
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 11
Parameter
Absolute Maximum Ratings
Symbol
Values
typ.
–
Unit
Note/ Test
Condition
min.
–0.5
max.
V
DDQ
+
0.5
+3.6
+3.6
+3.6
+70
+150
–
–
Voltage on I/O pins relative to
V
SS
V
IN
,
V
OUT
V
–
Voltage on inputs relative to
V
SS
Voltage on
V
DD
supply relative to
V
SS
Voltage on
V
DDQ
supply relative to
V
SS
Operating temperature (ambient)
Storage temperature (plastic)
Power dissipation (per SDRAM component)
Short circuit output current
V
IN
V
DD
V
DDQ
T
A
T
STG
P
D
I
OUT
–1
–1
–1
0
-55
–
–
–
–
–
–
–
1
50
V
V
V
°
C
°
C
W
mA
–
–
–
–
–
–
–
Table 12
Parameter
Input and Output Capacitances
Symbol
Values
typ.
–
–
–
Unit
Note/
Test Condition
min.
-2.0
–
2.0
max.
3.0
0.25
3.0
Input Capacitance: CK, CK
Delta Input Capacitance CK, CK
C
dI1
Input Capacitance: All other
input-only pins
Delta Input Capacitance: All
other input-only pins
Input/Output Capacitance: DQ,
DQS, DM
Delta Input/Output Capacitance :
DQ, DQS, DM
C
I1
pF
pF
pF
1)
1) These values are guaranteed by design and are tested on a sample base only.
V
DDQ
=
V
DD
= 2.5 V
±
0.2 V,
f
= 100 MHz,
T
A
= 25
°
C,
V
OUT(DC)
=
V
DDQ
/2,
V
OUT
(Peak to Peak) 0.2 V. Unused pins are tied to ground.
2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace
matching at the board level.
1)
C
I2
1)
C
dI2
–
–
0.5
pF
1)2)
C
IO
4.0
5.0
pF
1)
C
dIO
–
–
0.5
pF
1)
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