參數(shù)資料
型號(hào)： HYB25D128800AT-6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 15/79頁(yè)
文件大?。?/td> 2596K
代理商： HYB25D128800AT-6
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
15
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst
length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column
address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the
starting location within the block. The programmed burst length applies to both Read and Write bursts.
3.2.2
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in
Table 4
.
Burst Type
Notes:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.2.3
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and
the availability of the first burst of output data. The latency can be programmed 2, 2.5 or 3 clocks.
If a Read command is registered at clock edge
n
, and the latency is
m
clocks, the data is available nominally
coincident with clock edge
n
+
m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Read Latency
Table 4
Burst
Length
Burst Definition
Starting Column Address
A2
A1
Order of Accesses Within a Burst
Type = Sequential
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Type = Interleaved
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
2
4
0
0
1
1
0
0
1
1
0
0
1
1
8
0
0
0
0
1
1
1
1
相關(guān)PDF資料
PDF描述
HYB25D128800ATL-8 128 Mbit Double Data Rate SDRAM
HYB25D128400CC-6 128 Mbit Double Data Rate SDRAM
HYB25D128400CT-7 128 Mbit Double Data Rate SDRAM
HYB25D128800CT-6 128 Mbit Double Data Rate SDRAM
HYB25D128800CTL-6 128 Mbit Double Data Rate SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128800AT-7 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800AT-8 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:?128Mb (16Mx8) DDR200 (2-2-2)?
HYB25D128800ATL-6 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800ATL-7 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800ATL-8 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*