參數(shù)資料
型號： HYB25D128800AT-6
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit Double Data Rate SDRAM
中文描述： 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù)： 22/79頁
文件大?。?/td> 2596K
代理商： HYB25D128800AT-6
HYB25D128[400/800/160]A-[6/7/8]
128Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
22
Rev. 1.06, 2004-01
09192003-LFQ1-R60G
3.5.2
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are
initiated with a Read command, as shown on
Figure 8 "Read Command" on Page 22
.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge
at the completion of the burst, provided
t
RAS
has been satisfied. For the generic Read commands used in the
following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or
negative clock edge (i.e. at the next crossing of CK and CK).
Figure 9 "Read Burst: CAS Latencies (Burst
Length = 4)" on Page 23
shows general timing for each supported CAS latency setting. DQS is driven by the DDR
SDRAM along with output data. The initial low state on DQS is known as the read preamble; the low state
coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming
no other commands have been initiated, the DQs goes High-Z. Data from any Read burst may be concatenated
with or truncated with data from a subsequent Read command. In either case, a continuous flow of data can be
maintained. The first data element from the new burst follows either the last element of a completed burst or the
last desired data element of a longer burst which is being truncated. The new Read command should be issued
×
cycles after the first Read command, where
×
equals the number of desired data element pairs (pairs are required
by the
2n
prefetch architecture). This is shown on
Figure 10 "Consecutive Read Bursts: CAS Latencies (Burst
Length = 4 or 8)" on Page 24
. A Read command can be initiated on any clock cycle following a previous Read
command. Nonconsecutive Read data is illustrated on
Figure 11 "Non-Consecutive Read Bursts: CAS
Latencies (Burst Length = 4)" on Page 25
. Full-speed
Figure 12 "Random Read Accesses: CAS Latencies
(Burst Length = 2, 4 or 8)" on Page 26
within a page (or pages) can be performed as shown on
Page 23
.
Reads
Figure 8
Read Command
BA
HIGH
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
CKE
CS
RAS
CAS
WE
A10
BA0, BA1
Don’t Care
CA
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
EN AP
DIS AP
CK
CK
相關(guān)PDF資料
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HYB25D128800ATL-8 128 Mbit Double Data Rate SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128800AT-7 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800AT-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (16Mx8) DDR200 (2-2-2)?
HYB25D128800ATL-6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800ATL-7 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
HYB25D128800ATL-8 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM
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