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參數(shù)資料
| 型號： | HYB25D128323CL4.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 39/53頁 |
| 文件大?。?/td> | 1166K |
| 代理商： | HYB25D128323CL4.5 |
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Data Sheet
39
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Note:All entries assume the CKE was High during the preceding clock cycle
WRITE
RECOVERING
with Auto-
precharge
DESEL
NOP
BST
READ / READA
WRITE / WRITEA
ACT
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
NOP
BST
READ / READA
WRITE / WRITEA
ACT
PRE / PREAL
AREF / SREF
MRS / EMRS
DESEL
X
X
X
BA, CA, A8
BA, CA, A8
BA, RA
BA ,A8
X
OP-Code
X
X
X
BA, CA, A8
BA, CA, A8
BA, RA
BA ,A8
X
OP-Code
X
NOP (Precharge after
t
WR
)
NOP (Precharge after
t
WR
)
NOP (Precharge after
t
WR
)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after
t
RC
)
NOP (Idle after
t
RC
)
NOP (Idle after
t
RC
)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Idle after two clocks)
1),
2)
1)
1)
1)
REFRESH
11)
(EXTENDED
MODE
REGISTER
SET)
NOP
BST
READ / READA
WRITE / WRITEA
ACT
PRE / PREAL
AREF / SREF
MRS / EMRS
X
X
BA, CA, A8
BA, CA, A8
BA, RA
BA ,A8
X
OP-Code
NOP (Idle after two clocks)
NOP (Idle after two clocks)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
1) Illegal to bank specified states; function may be legal in the bank indicated by BAx, depending on the state of that bank
2) Must satisfy bus contention, bus turn around, write recovery requirements.
3) If both banks are idle, and CKE is inactive, the device will enter Power Down Mode. All input buffers except CKE, CLK and
CLK# will be disabled.
4) If both banks are idle, and CKE is deactivated coincidentally with an AutoRefresh command, the device will enter
SelfRefresh Mode. All input buffers except CKE will be disabled.
5) Illegal, if
t
RRD
is not satisfied.
6) Illegal, if
t
RAS
is not satisfied.
7) Must satisfy burst interrupt condition.
8) Must mask two preceding data bits with the DM pin.
9) Illegal, if
t
RCD
is not satisfied.
10) Illegal, if
t
WR
is not satisfied.
11) Illegal, if
t
RC
is not satisfied.
Table 11
Current State
Function Truth Table I
(cont’d)
Command
Address
Action
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128323C-L3.6 | 128 Mbit DDR SGRAM |
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| HYB25D128323C | 128 Mbit DDR SGRAM |
| HYB25D128323C-3 | 128 Mbit DDR SGRAM |
| HYB25D128400AT | 128 Mbit Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128400AT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR266A (2-3-3)? |
| HYB25D128400AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR200 (2-2-2)? |
| HYB25D128400ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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