參數(shù)資料
型號: HYB25D128323CL4.5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁數(shù): 35/53頁
文件大?。?/td> 1166K
代理商: HYB25D128323CL4.5
Data Sheet
35
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Figure 29
Write interrupted by Precharge
3.7
Operations and Functions
Table 9
Operation
Command Overview
Code
CKE
n-1
H
H
H
H
CKE
n
X
X
X
X
CS#
RAS# CAS# WE#
BA0
BA1
A8
A0-7
A9-11
X
X
Device Deselect
No Operation
Mode Register Setup
Extended Mode Register
Setup
Bank Activate
Read
Read with Auto
Precharge
Write Command
Write Command with
Auto Precharge
Burst Stop
Precharge Single Bank
Precharge All Banks
Auto Refresh
Self Refresh Entry
Self Refresh Exit
DESEL
NOP
MRS
MRS
H
L
L
L
X
H
L
L
X
H
L
L
X
H
L
L
X
X
0
1
X
X
0
0
X
X
OPCODE
OPCODE
ACT
READ
READA
H
H
H
X
X
X
L
L
L
L
L
H
H
H
L
H
H
H
BA
BA
BA
BA
BA
BA
Row Address
L
H
Col.
Col.
WRITE
WRITEA
H
H
X
X
L
L
L
H
H
L
H
H
BA
BA
BA
BA
L
H
Col.
Col.
BST
PRE
PREAL
AREF
SREFEN
SREFEX
H
H
H
H
H
L
L
X
X
X
H
L
H
H
L
L
L
L
L
H
L
H
L
L
L
L
X
H
H
H
H
L
L
X
H
L
L
L
H
H
X
H
X
BA
X
X
X
X
X
X
BA
X
X
X
X
X
X
L
H
X
X
X
X
X
X
X
X
X
X
X
D-in
2
CLK
Write
bank A
DQSx
DQx
D-in
0
Command
t
WR
DMx
NOP
NOP
NOP
PRE
Write
bank B
NOP
D-in
1
D-in
3
t
DQSS
NOP
D-in
0
D-in
1
Last valid
data
Data must be
masked
Data is masked
by Precharge
Burst length = 8
t
DQSS
D-in
4
D-in
5
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