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參數(shù)資料
| 型號(hào)： | HYB25D128323CL4.5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁(yè)數(shù)： | 26/53頁(yè) |
| 文件大?。?/td> | 1166K |
| 代理商： | HYB25D128323CL4.5 |
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HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
26
V1.7, 2003-07
Figure 18
Burst Write Operation
3.5.12
A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop
Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has
been completed. When the Burst Stop Command is issued during a burst read cycle, read data and DQSx go to
a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop
latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation.
Burst Stop is also illegal during Read with Auto-Precharge.
Burst Stop Command (BST)
CLK
WRITE
DQSx
DQx
Data-in
0
t
DQSS
t
WPREH
t
WPRES
t
WPST
Burst length = 4
NOP
NOP
NOP
Data-in
1
Data-in
2
Data-in
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128323C-L3.6 | 128 Mbit DDR SGRAM |
| HYB25D128323ACL-33 | JT 55C 55#22D SKT PLUG |
| HYB25D128323C | 128 Mbit DDR SGRAM |
| HYB25D128323C-3 | 128 Mbit DDR SGRAM |
| HYB25D128400AT | 128 Mbit Double Data Rate SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128400AT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR266A (2-3-3)? |
| HYB25D128400AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?128Mb (32Mx4) DDR200 (2-2-2)? |
| HYB25D128400ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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