參數(shù)資料
型號(hào)： HYB25D128323CL4.5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 33/53頁(yè)
文件大小： 1166K
代理商： HYB25D128323CL4.5
Data Sheet
33
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.6.3
A Burst Read operation can be interrupted by a Precharge of the same bank. The Read command to Precharge
time is minimum 1 clock cycle. The Precharge command disables the data output depending on the CAS latency.
Once the last data bit has been outputted, the output buffers are tristated. A new Bank Activate command may be
issued to the same bank after
t
RP
.
Read Interrupted by a Precharge
Figure 26
Read interrupted by Precharge
3.6.4
A Burst Write can be interrupted before completion of the burst by a new Write Command. The minimum distance
between two different Write commands is one clock cycle. When the previous burst is interrupted, the remaining
addresses are overridden by the new address and data will be written into the device until the programmed burst
length is satisfied. The Write to Write interval (CAS a to CAS b command period) is defined by the parameter
t
CCD
.
Write Interrupted by a Write
Figure 27
Write interrupted by Write
CLK
READ
DQSx
DQx
D-out
0
Command
NOP
PRE
NOP
NOP
ACT
D-out
1
Burst length = 8
CL = 2
NOP
Precharge latency = CL
D-out
2
D-out
3
tRP
First possible
ACT command
CLK
WRITE a
DQSx
DQx
D-in
a0
Command
WRITE b
NOP
NOP
NOP
D-in
a1
D-in
b1
tCCD
Burst length = 4
D-in
b0
D-in
b3
D-in
b2
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