參數(shù)資料
型號: HYB25D128323CL3.6
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit DDR SGRAM
中文描述: 128兆的DDR SGRAM
文件頁數(shù): 40/53頁
文件大小: 1166K
代理商: HYB25D128323CL3.6
X
X
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Data Sheet
40
V1.7, 2003-07
Table 12
Current
State
SELF
REFRESH
Function Truth Table for CKE
CKE
n-1
n
H
X
X
L
H
H
L
H
L
L
H
L
L
H
L
L
H
L
L
L
X
H
X
X
L
H
X
L
L
X
H
H
X
H
L
L
H
L
H
H
L
L
H
L
L
H
L
L
H
L
L
L
X
X
H
H
X
CKE
CS#
RAS
#
X
X
H
H
H
L
X
X
X
X
X
L
X
H
H
H
L
X
X
CAS
#
X
X
H
H
H
L
X
X
X
X
X
L
X
H
H
L
X
X
X
WE#
Address Action
Notes
X
X
H
X
X
X
X
X
X
X
X
H
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self-Refresh ( Idle after
t
SRX
)
Exit Self-Refresh ( Idle after
t
SRX
)
ILLEGAL
ILLEGAL
ILLEGAL
NOP ( Maintain Self Refresh)
INVALID
Exit Power Down ( Idle after
t
PDEX
)
NOP ( Maintain Power Down)
Refer to Function Truth Table
Enter Self Refresh
Enter Power-Down
Enter Power-Down
ILLEGAL
ILLEGAL
ILLEGAL
Refer to Power Down in this table
Refer to Funtion Truth Table
1)
1) CKE low-to-high transition re-enables inputs asynchronously. A minimum setup time to CLK must be satisfied before any
commands other than EXIT are executed.
2) Power Down can be entered when all banks are idle (banks can be active or precharged)
3) Self Refresh can be entered only from the Precharge / Idle state.
1)
1)
1)
1)
1)
1)
POWER
DOWN
ALL
BANKS
IDLE
2)
3)
2)
2)
2)
2)
2)
All other
states
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