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參數(shù)資料
| 型號： | HYB25D128323CL3.6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit DDR SGRAM |
| 中文描述： | 128兆的DDR SGRAM |
| 文件頁數(shù)： | 21/53頁 |
| 文件大小： | 1166K |
| 代理商： | HYB25D128323CL3.6 |
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Data Sheet
21
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
3.5.4
The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR
SGRAM has four independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank
Activation command must be applied before any Read or Write operation can be executed. The delay from the
Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS
delay time (
t
RCDDC
min
.
for read commands and
t
RCDWR
min. for write commands). Once a bank has been activated,
it must be precharged before another Bank Activate command can be applied to the same bank. The minimum
time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank
activation delay time (
t
RRD
min).
Bank Activation Command (ACT)
Figure 11
Activate to Read or Write Command Timing (one bank)
Figure 12
Activate Bank A to Activate Bank B Timing
3.5.5
This command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a
Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each
bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be
precharged. After a Precharge command, the analog delay
t
RP
has to be met until a new Activate command can
be initiated to the same bank.
Precharge Command
Clk
Command
t
RCDWR for write
Bank A
Row Add.
ACT
t
RCDRD for read
t
RC
Addresses
Ror
WRITE
Bank A
Col. Add.
Bank A
PRE
NOP
ACT
Bank A
Row Add.
Clk
Command
Bank B
Row Add.
ACT
t
RRD
Addresses
NOP
ACT
Bank A
Row Add.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128323C-3.3 | 128 Mbit DDR SGRAM |
| HYB25D128323C-3.6 | 128 Mbit DDR SGRAM |
| HYB25D128323C-4.5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-5 | 128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 128 Mbit DDR SGRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128323CL4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323C-L4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128323CL-4.5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM |
| HYB25D128400AT | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128400AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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