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參數(shù)資料
| 型號： | HYB 5117805BSJ-60 |
| 廠商： | SIEMENS AG |
| 英文描述： | 2M×8 - Bit Dynamic RAM 2k Refresh（Hyper Page Mode EDO） |
| 中文描述： | 200萬× 8 -位動態(tài)隨機存儲器（200萬× 8位動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 176K |
| 代理商： | HYB 5117805BSJ-60 |
HYB 5(3)117805/BSJ-50/-60
2M
×
8 EDO-DRAM
Semiconductor Group
9
1998-10-01
Notes
1. All voltages are referenced to
V
SS
.
2.
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3.
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4. Address can be changed once or less while RAS =
V
IL
. In case of
I
CC4
it can be changed once
or less during a hyper page mode (EDO) cycle
5. An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least
one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using
the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8
RAS cycles are required.
6. AC measurements assume
t
T
= 2 ns.
7.
V
IH (MIN.)
and
V
IL (MAX.)
are reference levels for measuring timing of input signals. Transition times
are also measured between
V
IH
and
V
IL
.
8. Measured with the specified current load and 100 pF at
V
OL
= 0.8 V and
V
OH
= 2.0 V. Access
time is determined by the latter of
t
RAC
,
t
CAC
,
t
AA
,
t
CPA
,
t
OEA
.
t
CAC
is measured from tristate.
9. Operation within the
t
RCD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RCD (MAX.)
is specified as
a reference point only. If
t
RCD
is greater than the specified
t
RCD (MAX.)
limit, then access time is
controlled by
t
CAC
.
10.Operation within the
t
RAD (MAX.)
limit ensures that
t
RAC (MAX.)
can be met.
t
RAD (MAX.)
is specified as
a reference point only. If
t
RAD
is greater than the specified
t
RAD (MAX.)
limit, then access time is
controlled by
t
AA
.
11.Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12.
t
OFF (MAX.)
,
t
OEZ (MAX.)
define the time at which the output achieves the open-circuit conditions and
are not referenced to output voltage levels.
t
OFF
is referenced from the rising edge of RAS or
CAS, whichever occurs last.
13.Either
t
DZC
or
t
DZO
must be satisfied.
14.Either
t
CDD
or
t
ODD
must be satisfied.
15.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only. If
t
WCS
>
t
WCS (MIN.)
, the cycle is an early write cycle and
data out pin will remain open-circuit (high impedance) through the entire cycle; if
t
RWD
>
t
RWD (MIN.)
,
t
CWD
>
t
CWD (MIN.)
and
t
AWD
>
t
AWD (MIN.)
, the cycle is a read-write cycle and I/O will
contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the
condition of I/O (at access time) is indeterminate.
16.These parameters are referenced to the CAS leading edge in early write cycles and to the WE
leading edge in read-write cycles.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB3117805BSJ-60 | 2M x 8-Bit Dynamic RAM 2k Refresh |
| HYB314405BJBJL-50- | 1M x 4-Bit Dynamic RAM |
| HYB314405BJ-60 | Transistor Array IC; Number of Transistors:4; Package/Case:16-SOIC; C-E Breakdown Voltage:50V; Mounting Type:Surface Mount |
| HYB314405BJ-70 | 1M x 4-Bit Dynamic RAM |
| HYB 314405BJ | 1M × 4-Bit Dynamic RAM(Fast Page Mode)(1M x 4位 動態(tài) RAM(快速頁面模式)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB5117805BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8-Bit Dynamic RAM 2k Refresh |
| HYB5118160BSJ50 | 制造商:SIEMENS 功能描述:* |
| HYB5118160BSJ-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM |
| HYB5118160BSJ-50- | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k Refresh |
| HYB5118160BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1M x 16-Bit Dynamic RAM 1k Refresh |
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