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參數(shù)資料
| 型號： | HY628400A |
| 英文描述： | 512Kx8bit CMOS SRAM(512Kx8位 CMOS 靜態(tài)RAM) |
| 中文描述： | 512Kx8bit的CMOS的SRAM（512Kx8位的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 130K |
| 代理商： | HY628400A |
HY628400A Series
Rev.03 / Jun. 2000
7
Notes:
1. A write occurs whenever a low on the /WE and /OE is low while /CS are in active state.
2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the
output must not be applied.
4. If the /CS low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. /OE is continuously low(/OE=V
IL
)
6. Q(data out) is the same phase with the write data of this write cycle.
7. Q(data out) is the read data of the next address.
8. Transition is measured + 200mV from steady state.
This parameter is sampled and not 100% tested.
9. /CS in high for the standby, low for active
DATA RETENTION ELECTRIC CHARATERISTIC
T
A
=0
°
C to 70
°
C (Normal)
Symbol
V
DR
Vcc for Data Retention
Parameter
Test Condition
/CS > Vcc - 0.2V
Vss<V
IN
<Vcc
Vcc = 3.0V,
/CS >Vcc - 0.2V
Vss<V
IN
<Vcc
Min
2.0
Typ
-
Max
-
Unit
V
I
CCDR
L
LL
-
-
-
-
50
15
uA
uA
Data Retention Current
tCDR
tR
Chip Deselect to Data Retention Time
Operating Recovery Time
0
-
-
-
-
ns
ns
tRC(2)
Notes:
1. Typical values are at the condition of T
A
= 25
°
C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
/CS
VDR
/CS > VCC-0.2V
tCDR
tR
VSS
VCC
4.5V
2.2V
DATA RETENTION MODE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY628400ALG | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512K x8 bit 5.0V Low Power CMOS slow SRAM |
| HY628400ALG-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628400ALG-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628400ALG-85 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| HY628400ALG-E | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512K x8 bit 5.0V Low Power CMOS slow SRAM |
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