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參數(shù)資料
| 型號： | HY5DU28422BLT-X |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | 128M-S DDR SDRAM |
| 中文描述： | 128M的，擰DDR SDRAM內存 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大?。?/td> | 343K |
| 代理商： | HY5DU28422BLT-X |
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DESCRIPTION
The Hynix HY5DU28422B(L)T and HY5DU28822B(L)T are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and high band-
width.
The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
V
DD
, V
DDQ
= 2.5V +/- 0.2V
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
On chip DLL align DQ and DQS transition with CK
transition
DM mask write data-in at the both rising and falling
edges of the data strobe
tRAS Lock-out function supported
All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
Programmable /CAS latency 2 and 2.5 supported
Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed
/RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* X means speed grade
Part No.
Configuration
PACKAGE
HY5DU28422B(L)T-X*
32Mx4
400mil
66pin
TSOP-II
HY5DU28822B(L)T-X*
16Mx8
PRELIMINARY
Rev. 0.3/May. 02 3
OPERATING FREQUENCY
Grade
CL2
CL2.5
Remark
(CL-tRCD-tRP)
- J
133MHz
166MHz
DDR333 (2.5-3-3)
-M
133MHz
133MHz
DDR266 (2-2-2)
- K
133MHz
133MHz
DDR266A (2-3-3)
- H
100MHz
133MHz
DDR266B (2.5-3-3)
- L
100MHz
125MHz
DDR200 (2-2-2)
HY5DU28422B(L)T
HY5DU28822B(L)T
相關PDF資料 |
PDF描述 |
|---|---|
| HY5DU28422BT-X | 128M-S DDR SDRAM |
| HY5DU28822BLT-X | 128M-S DDR SDRAM |
| HY5DU28822BT-X | 128M-S DDR SDRAM |
| HY5DU561622DLTP | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
| HY5DU561622DLTP-H | 256M DDR SDRAM (268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU28422BT | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M-S DDR SDRAM |
| HY5DU28422BT-H | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X8MX4|CMOS|TSSOP|66PIN|PLASTIC |
| HY5DU28422BT-J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X8MX4|CMOS|TSSOP|66PIN|PLASTIC |
| HY5DU28422BT-K | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X8MX4|CMOS|TSSOP|66PIN|PLASTIC |
| HY5DU28422BT-L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|DDR|4X8MX4|CMOS|TSSOP|66PIN|PLASTIC |
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