參數(shù)資料
型號: HW-V5GBE-DK-UNI-G-PROMO1
廠商: Xilinx Inc
文件頁數(shù): 10/91頁
文件大?。?/td> 0K
描述: KIT DEV V5 LXT GIGABIT ETHERNET
產(chǎn)品變化通告: Product Notice_Dev Systems Product
標(biāo)準(zhǔn)包裝: 1
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
18
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
FGTPRX
Serial data rate
RX oversampler not enabled
0.5
FGTPMAX
Gb/s
RX oversampler enabled
0.1
0.5
Gb/s
RXOOBVDPP
OOB detect threshold
peak-to-peak
OOBDETECT_THRESHOLD = 100
60
105
165
mV
RXSST
Receiver spread-spectrum
tracking(1)
Modulated @ 33 KHz
–5000
0
ppm
RXRL
Run length (CID)
Internal AC capacitor bypassed
150
UI
RXPPMTOL
Data/REFCLK PPM offset
tolerance(2)
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 1(3)
–200
200
ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 2(3)
–200
200
ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 4(3)
–100
100
ppm
CDR 2nd-order loop enabled
–1000
1000
ppm
SJ Jitter Tolerance(4)
JT_SJ3.75
Sinusoidal Jitter(5)
3.75 Gb/s
0.30
UI
JT_SJ3.2
Sinusoidal Jitter(5)
3.20 Gb/s
0.40
UI
JT_SJ2.50
Sinusoidal Jitter(5)
2.50 Gb/s
0.40
UI
JT_SJ2.00
Sinusoidal Jitter(5)
2.00 Gb/s
0.40
UI
JT_SJ1.00
Sinusoidal Jitter(5)
1.00 Gb/s
0.30
UI
JT_SJ500
Sinusoidal Jitter(5)
500 Mb/s
0.30
UI
JT_SJ500
Sinusoidal Jitter(5)
500 Mb/s OS
0.30
UI
JT_SJ100
Sinusoidal Jitter(5)
100 Mb/s OS
0.30
UI
SJ Jitter Tolerance with Stressed Eye(4)
JT_TJSE3.2
Total Jitter with Stressed
Eye(6)
3.20 Gb/s
0.87
UI
JT_SJSE3.2
Sinusoidal Jitter with
Stressed Eye(6)
3.20 Gb/s
0.30
UI
Notes:
1.
Using PLL_RXDIVSEL_OUT = 1 only.
2.
Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3.
CDR 1st-order step size set to 2.
4.
All jitter values are based on a Bit Error Ratio of 1e–12.
5.
Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
6.
Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
相關(guān)PDF資料
PDF描述
RSM10DRSI-S288 CONN EDGECARD 20POS DIP .156 SLD
MAX6440UTNTYD7+T IC BATTERY MON SNGL SOT23-6
VI-B02-EY-F4 CONVERTER MOD DC/DC 15V 50W
MAX6441KABGYD7+T IC BATTERY MON DUAL SOT23-8
HW-SPAR3ADDR2-DK-UNI-G-PROMO1 KIT DEV SPARTAN 3A DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HW-V5GBE-DK-UNI-G-PROMO2 功能描述:KIT DEV V5 LXT GIGABIT ETHERNET RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:- 傳感器類型:CMOS 成像,彩色(RGB) 傳感范圍:WVGA 接口:I²C 靈敏度:60 fps 電源電壓:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相關(guān)產(chǎn)品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP
HW-V5-ML501-UNI-G 功能描述:EVALUATION PLATFORM VIRTEX-5 RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件(MCU、DSP、FPGA、CPLD等) 系列:Virtex®-5 LX 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206,PIC16F690,PIC16F819 所含物品:板,線纜,元件,CD,PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
HW-V5-ML501-UNI-G-J 功能描述:EVALUATION PLATFORM VIRTEX-5 RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件(MCU、DSP、FPGA、CPLD等) 系列:Virtex®-5 LX 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206,PIC16F690,PIC16F819 所含物品:板,線纜,元件,CD,PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)
HW-V5-ML505-UNI-G 制造商:Xilinx 功能描述:HARDWARE, VIRTEX-5 ML505 EVALUATION PLATFORM, UNIVERSAL - Bulk 制造商:Xilinx 功能描述:XLXHW-V5-ML505-UNI-G EVALUATION KIT 制造商:Xilinx 功能描述:KIT EVAL PLATFORM VIRTEX-5 LXT ML505
HW-V5-ML505-UNI-G-J 功能描述:VIRTEX-5 LXT ML505 EVAL PLATFORM RoHS:是 類別:編程器,開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件(MCU、DSP、FPGA、CPLD等) 系列:Virtex®-5 LXT 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206,PIC16F690,PIC16F819 所含物品:板,線纜,元件,CD,PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF)