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參數(shù)資料
| 型號： | HV7131RP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 9/61頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | HV7131RP |
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HV7131GP
2004/10/29 V2.4 9
Functional Description
Pixel Architecture
Pixel architecture is a 4 transistor NMOS pixel design. The additional use of a dedicated transfer
transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible.
Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel
sensitivity is achieved.
ENB Setting guide information for normal stand-by mode
It is necessary that this kind of initialization sequence for the normal stand-by mode of HV7131GP after
system power on
DVDD/AVDD
RESETB
MCLK
VSYNC
I2C
ENB
Don’t care
Low
Low
Low
Low
System power On
Initialization sequence
2.086 [Mcycle] for logic stable time
2.0 [Mcycle] for 1'st VSYNC out
More than 4cycle
Don’t care
1ms
Sensor operation sequence
Sensor Power down sequence
Camera Mode
Video stream
1’st VSYNC out
1[ms] or more
ex) If MCLK = 25[Mhz]
=> 2.086[Mcycle] / 25[MHz] = 83.44 ms
The time period of ENB high value have to keep for 83.44[ms] or more
Sensor Imaging Operation
Imaging operation is implemented by the offset mechanism of integration domain and scan
domain(rolling shutter scheme). First integration plane is initiated, and after the programmed integration
time is elapsed, scan plane is initiated, then image data start being produced.
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