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| 型號： | HV7131RP |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Image Sensor with Image Signal Processing |
| 中文描述： | 的CMOS圖像傳感器和圖像信號處理 |
| 文件頁數(shù)： | 27/61頁 |
| 文件大?。?/td> | 2621K |
| 代理商： | HV7131RP |
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HV7131GP
2004/10/29 V2.4 27
to low, R/G/B channels for one pixel are fed with the same one Bayer value
so that image similar to black & white is produced.
Gamma Correction
With this bit set to high, 10 segments piecewise approximate gamma is
enabled.
Output Format [OUTFMT : 31h : 39h]
7
6
5
4
3
2
1
0
Gamma-
corrected
Bayer
Bayer 8bit
output
Cb First
Y First
8 Bit Output
reserved
YCbCr
4:4:4
YCbCr
4:2:2
0
0
1
1
1
0
0
1
Gamma-corrected
Bayer
Bayer data that are gamma corrected is output when Bayer mode is set in
SCTRA register.
Bayer 8bit output
Bayer data is output with 8bit mode. two LSB of 10 bit Bayer data is
stripped out.
Cb First
Cb pixel in front of Cr pixel in 16bit or 8bit video data output modes
Y First
Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is
meaningful only with 8bit output mode.
8 Bit Output
Image Data is produced only in Y[7:0]. C[7:0] should be discarded
YCbCr 4:4:4
YCbCr 24bit data for a pixel is produced with 16bit output mode. With color
space conversion disabled, RGB 24bit data for a pixel is produced in this
mode. This mode is meaningful only with 16bit output mode.
YCbCr 4:2:2
YCbCr data for a pixel is produced with 8/16 output mode
Output Inversion[OUTINV : 32h : 0h]
7
6
5
4
3
2
1
0
reserved
Clocked
HSYNC
VSYNC
inversion
HSYNC
inversion
VCLK
inversion
0
0
0
0
0
0
0
0
Clocked HSYNC
In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate
during normal HSYNC time
VSYNC inversion
VSYNC output polarity is inverted
HSYNC inversion
HSYNC output polarity is inverted
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