參數(shù)資料
型號(hào): HT47C10L
英文描述: 8-Bit R-F Type Low Voltage Mask MCU
中文描述: 8位低電壓RF型微控制器面具
文件頁(yè)數(shù): 7/38頁(yè)
文件大?。?/td> 287K
代理商: HT47C10L
HT47C10L
Rev. 1.10
7
October 2, 2002
Program memory
ROM
The program memory is used to store the program in-
structions, which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
1024 16 bits, addressed by the program counter and
table pointer.
Certain locations in the program memory are reserved
for special usage:
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
Location 004H
This area is reserved for the timer/event counter inter-
rupt service program. If timer interrupt results from a
timer/event counter A or B overflow, and if the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 004H.
Location 008H
This area is reserved for the time base interrupt ser-
viceprogram.Ifatimebaseinterruptoccurs,andifthe
interrupt is enabled and the stack is not full, the pro-
gram begins execution at location 008H.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
theTBLH.Thetablehigher-orderbyteregister(TBLH)
is read only. The table pointer (TBLP) is a read/write
register (07H), which indicates the table location. Be-
fore accessing the table, the location must be placed
in TBLP. The TBLH is read only and cannot be re-
stored. If the main routine and the ISR (interrupt ser-
vice routine) both employ the table read instruction,
the contents of the TBLH in the main routine are likely
to be changed by the table read instruction used in the
ISR. Errors can occur. In other words using the table
read instruction in the main routine and the ISR simul-
taneously should be avoided. However, if the table
readinstructionhastobeappliedinboththemainrou-
tine and the ISR, the interrupt is supposed to be dis-
abled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon the requirements.
Stack register
STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into two levels and is neither part of
the data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledg-
ment, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
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Program memory
Instruction(s)
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *9~*0: Bits of table location
@7~@0: Bits of table pointer
P9 P8: Bits of current program counter
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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