HT47C10L
Rev. 1.10
11
October 2, 2002
Time base
TB
The time base is used to supply a regular internal inter-
rupt. Its time-out period ranges from f
s
/2
8
to f
s
/2
15
by
software programming. Writing data to RT2, RT1 and
RT0 (bits 2, 1, 0 of TBC;09H) yields various time-out
periods. If a time base time-out occurs, the related inter-
rupt request flag (TBF; bit 5 of INTC) is set. But if the in-
terrupt is enabled, and the stack is not full, a subroutine
call to location 08H occurs. When the HALT instruction
is executed, the time base still works and can wake-up
from HALT mode if f
OSC
is on. If the TBF is set 1 before
entering the HALT mode, the wake-up function will be
disabled.
RT2
RT1
RT0
Time Base
Divided Factor
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Power down operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following.
The f
OSC
and f
SYS
will still work or stop depend on
STANDBY option (Option register bit 5), but T1 will
turn off.
The contents of the on-chip RAM and registers remain
unchanged.
The WDT will be cleared and recount again.
All I/O ports maintain their original status.
The PD flag is set and the TO flag is cleared.
LCD driver can be off or on depend on STANDBY op-
tion (Option register bit 5)
The time base will stop or run depends on STANDBY
option (Option register bit 5).
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Awaken-
ing from an I/O port stimulus, the program will resume
execution of the next instruction. If awakening from an
interrupt, two sequences may happen. If the related in-
terrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, a regular interrupt response takes place.
If an interrupt request flag is set to 1 before entering
the HALT mode the wake-up function of the related in-
terrupt will be disabled.
If the wake-up results from an interrupt acknowledg-
ment, the actual interrupt subroutine execution will be
delayed by more than one cycle. However, if the
wake-up results in the next instruction execution, the ex-
ecution will be performed immediately.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT mode.
Reset
There are three ways in which a reset may occur.
RES reset during normal operation
RES reset during HALT mode
WDT time-out reset during normal operation
The WDT time-out during HALT mode is different from
other chip reset conditions, since it can perform a warm
reset that just resets the PC and SP leaving the other
circuits in their original state. Some registers remain un-
changed during other reset conditions. Most registers
are reset to the initial condition when the reset condi-
tions are met. By examining the PD and TO flags, the
programcandistinguishbetweendifferent chipresets .
TO
PD
RESET Conditions
0
0
System power-up
u
u
RES reset or LVR reset during normal
operation
0
1
RES reset or LVR reset wake-up from
HALT mode
1
u
WDT time-out during normal operation
1
1
WDT wake-up from HALT mode
Note: u means unchanged
The chip-reset status of the functional units are shown be-
low.
PC
000H
Interrupt
Disabled
Prescaler, Divider
Cleared
WDT, Time Base
Clear. After master reset,
begin counting
Timer/event Counter
Off
Input/output Ports
Input mode
SP
Points to the top of the stack