HT47C10L
Rev. 1.10
13
October 2, 2002
Timer/event counter
One16-bittimer/eventcounterorRCtypeA/Dconverter
is implemented in the HT47C10L. The ADC/TM bit (bit 1
of ADCR register) decides whether timer A and timer B
are composed of one 16-bit timer/event counter or timer
AandtimerBarecomposedofRCtypeA/Dconverter.
The TMRAL, TMRAH, TMRBL, TMRBH composed of
one 16-bit timer/event counter, when ADC/TM bit is 0 .
The TMRBL and TMRBH are timer/event counter
preload registers for lower-order byte and higher-order
byte respectively.
The timer/event counter clock source comes from system
clock (f
SYS
) or external source (A/D clock from pad:RCIN).
The external clock input allows the user to count external
events,countexternalRCtypeA/Dclock,measuretimein-
tervalsorpulsewidths,orgenerateanaccuratetimebase.
There are six registers related to the timer/event counter
operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC
([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR
([25H]). Writing to TMRBL only writes the data into a low
byte buffer, and writing to TMRBH will write the data and
thecontentsofthelowbytebufferintothetime/eventcoun-
ter preload register (16-bit) simultaneously. The
timer/event counter preload register is changed by writ-
ingtoTMRBHoperationsandwritingtoTMRBLwillkeep
thetimer/eventcounterpreloadregisterunchanged.
Reading TMRAH will also latch the TMRAL into the low
byte buffer to avoid the false timing problem. Reading
TMRAL returns the contents of the low byte buffer. In
other words, the low byte of the timer/event counter can
not be read directly. It must read the TMRAH first to
make the low byte contents of timer/event counter be
latched into the buffer.
The TMRC is the timer/event counter control register,
which defines the timer/event counter options. The
timer/event counter control register define the operating
mode, counting enable or disable and active edge. Writ-
ing to timer B location puts the starting value in the
timer/event counter preload register, while reading timer
A yields the contents of the timer/event counter. Timer B
is timer/event counter preload register.
The TN0 and TN1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source (A/D clock) comes
from an external (RCIN) pin. The timer mode functions
as a normal timer with the clock source coming from the
internal clock source (f
SYS
). Finally, the pulse width
measurement mode can be used to count the high or
low level duration of the external signal (A/D clock from
pad:RCIN). The counting is based on the system clock
(f
SYS
).
In the event count, A/D clock or internal timer mode,
once the timer/event counter starts counting, it will count
from the current contents in the timer/event counter
(TMRAH and TMRAL) to FFFFH. Once overflow occurs,
the counter is reloaded from the timer/event counter
preload register (TMRBH and TMRBL) and generates
the corresponding interrupt request flag (TF; bit 4 of
INTC) at the same time.
In the pulse width measurement mode with the TON
and TE bits equal to one, once the RCIN has received a
transient from low to high (or high to low if the TE bit is
0) it will start counting until the A/D Clock returns to the
original level and resets the TON. The measured result
will remain in the timer/event counter even if the acti-
vated transient occurs again. In other words, only one
cycle measurement can be done. Until setting the TON,
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Timer/event counter