參數(shù)資料
型號: HSP50214AVI
廠商: HARRIS SEMICONDUCTOR
元件分類: 通信及網(wǎng)絡
英文描述: Programmable Downconverter
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁數(shù): 55/60頁
文件大小: 467K
代理商: HSP50214AVI
55
24
Test Circuit Disable
The A Version includes test circuitry for the ROM and RAM blocks that was not present in the orig-
inal release part. This circuitry must be disabled before loading the coefficient RAM’s. This is done
by setting bit 24 to zero.
NOTE: Because the HSP50214 did not require a “write” to Control Word 25 and the
HSP50214A does require that Control Word 25, Bit 24 be set to zero for normal
operation, software that was written for the HSP50214 will require modification to
work properly with the HSP50214A.
CONTROL WORD 26: LOAD AGC GAIN (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
AGC Load
Writing to this location generates a strobe to load the AGC loop accumulator with bits (15:5) to
the master registers. These bits are loaded into the MSBs of the AGC loop filter accumulator
with bits (15:12) mapping to the shift (exponent) control bits and bits (11:5) mapping to the mul-
tiplier (mantissa) bits. Bits (11:5) represent a binary mantissa mapped to the linear gain as:
01.XXXXXXX. See AGC Section.
CONTROL WORD 27: TEST REGISTER (SYNCHRONIZED TO CLKIN)
BIT
POSITION
FUNCTION
DESCRIPTION
31-25
Reserved
A fixed value of 0000 000 is loaded here for normal operation.
24
RAM Test Enable
0 = Normal Operation; 1 = RAM Test Enabled.
23
Input Level Detector
Counter Preload
Select
0 = The two LSB’s of the interpolation period preload are set to zero.
1 = The two LSB’s of the interpolation period preload are set to one.
22
SYNCIN1 Reset
Control
0: SYNCIN1 causes only front end reset.
1: SYNCIN1 causes front end and back end resets.
21
Timing Error Input
Select
0 = Operates as HSP50214.
1 = Corrects an error in the 4 LSB’s.
20
Timing NCO Reset
Control Select
0 = Backend reset will not clear the timing NCO phase accumulator feedback.
1 = Backend reset clears the timing NCO phase accumulator.
19 - 18
Discriminator FIR
Input
00 = 18 bits of delayed and subtracted (optionally shifted) phase.
01 = 18 bits of magnitude from coordinate converter.
1X = 18 bits of resampler/halfband filer I output.
17
Input Level Detector
Integration Start
Select
0 = No external sync control of input end detector start/restart of integration period.
1 = SYNCIN causes the input level detector to start/restart its integration period.
16
AGC Average
Control
0: AGC settles to mean.
1: AGC settles to median.
15
AGC Clear Inhibit
When set to zero, this bit will clear the AGC loop filter accumulator on a SYNCIN2 assertion or
a WRITE to CW 25.
When set to a one, a WRITE to CW25 will not clear the AGC loop filter accumulator.
14
Q Input to Coordi-
nate Converter (see
bits 19 - 15)
0 = I and Q enabled to coordinate converter.
I = Q input to coordinate converter is zeroed.
13
Coordinate Convert-
er Input
0 = The Resampler HB filter output is routed to coordinate converter.
1 = The output of 255 tap FIR is routed to coordinate converter.
12-0
Reserved
A fixed value 0 0010 0111 1000 [0278]hex is loaded here for normal operation.
A fixed value 0 0010 0111 1010 [027A]hex is loaded here for setting the Sin/Cos Generator out-
puts to 7FFF.
CONTROL WORD 25: COUNTER AND ACCUMULATOR RESET (SYNCHRONIZED TO BOTH CLKIN AND PROCCLK) (Continued)
BIT
POSITION
FUNCTION
DESCRIPTION
HSP50214A
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