參數(shù)資料
型號： HSP50214AVI
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁數(shù)： 30/60頁
文件大?。?/td> 467K
代理商： HSP50214AVI
30
The magnitude resolution may suffer because there is no
gain adjustment before computing the magnitude. If the sig-
nal is < - 90dBFS, it will be below the LSB of the magnitude
output.
The enable signal for gating data into the coordinate con-
verter is either the AGC data ready signal or the resampler
data ready signal. If the resampler is bypassed, the AGC
data ready signal is used and there is a delay of 6 clock
cycles between the FIR data being ready and the coordinate
converter block sampling it. If the resampler is enabled, its
data ready signal will be delayed by 6 clocks (for the AGC)
plus the compute delay of the resampler block. This may
cause the I/Q to |r|/
θ
output sample alignment to shift with
decimation. For this reason, it is recommended that the res-
ampler/halfband filter block be bypassed when using this
new data path.
To select the output of the 255 tap programmable FIR filter to
be routed to the coordinate converter, set Control Word 27,
Bit 13 to a logic one. For routing as in the HSP50214, set
Control Word 27, Bit 13 to a logic zero.
Frequency Discriminator
The discriminator block delays phase from the Cartesian to
Polar Section and subtracts it from the latest sample. This
delay and subtract can be modeled as a programmable
delay comb filter. The output of the filter is d
θ
/dt, or fre-
quency. The transfer function of the discriminator is set by
where D is the programmable discriminator delay expressed
in number of sample clock delays. The discriminator output
frequency is then filtered with a programmable FIR filter. The
Block Diagram of the Frequency Discriminator is shown in
Figure 29.
The range of delay in the discriminator is from 1 to 8 sam-
ples. Modulo 2
π
subtraction eliminates rollover problems in
the subtraction at 2
π
. The alias free discriminator frequency
range is given by:
where D is the discriminator delay defined in Equation 21
(1 < D < 8), F
SAMPOUT
is the Discriminator FIR filter output
sample rate and CW is the desired center frequency. When
the phase multiplier is set to a value other than 2
0
, the dis-
criminator range is reduced proportionally. The phase multi-
plier can be 1, 2, 4 or 8 (2
0
to 2
3
). Thus, a multiply of 2
1
reduces the range by 2, a multiply of 2
2
reduces the range
by 4, and a multiply of 2
3
reduces the range by 8.
The FIR filter can be configured with up to 63 symmetric taps
and up to 32 asymmetric taps. In the symmetric mode, the
FIR can be configured for even or odd symmetry, as well as
with an even or odd number of filter taps. Decimation is pro-
vided to allow more processing time for longer (i.e., more
taps) filter structures.
The HSP50214A offers an expanded choice of signals to be
filtered by the discriminator FIR. The choices are:
1) 18 bits of delayed, and subtracted (and optionally shifted)
phase. This is the Discriminator FIR filter input found in the
HSP50214.
2) 18 bits of magnitude from the coordinate converter block.
This was added to provide for post-detection filtering of AM
signals.
3) 18 bits from the I output of the resampler/interpolation
halfband filter block. This was added to provide for process-
ing of SSB signals.
The shift, delay, and subtract functions are bypassed for
items (2) and (3).
In addition to the FIR input selections, the Q input to the
coordinate converter block can be zeroed so that the magni-
tude output is the magnitude of I only. Again this was added
to provide for processing SSB signals.
The Discriminator FIR filter input selections are made in
Control Word 27, Bits 18 and 19. The bit definitions are:
00
Item (1) described above.
01
Item (2) described above.
1X
Item (3) described above.
Control Word 27, Bit 14 is used to control the Q input to the
coordinate converter. The bit definitions is:
0
I and Q enabled to the I/Q to R/Theta block.
1
The Q input to the I/Q to R/Theta block is zeroed.
The enable signals associated with the various input selec-
tions to the Discriminator FIR filter are:
1
The data ready strobe from the coordinate con-
verter block.
2
The data ready strobe from the coordinate con-
verter block.
(EQ. 21)
H z
1
Z
D
–
–
=
(EQ. 22)
Range
FREQDISC
CW
F
±
SAMPOUT
D
1
+
(
)
;
=
+
DELAY
(1-8)
-
63-TAP
FIR
FILTER
PHASE INPUT
PHASE MULTIPLIER
DISCRIMINATOR DELAY
DISCRIMINATOR EN
DISC. FIR DECIMATION
FIR SYMMETRY TYPE
FIR SYMMETRY
FIR TAPS
FIR COEFFICIENTS
FREQ(15:0)
Controlled via microprocessor interface.
FIGURE 29. FREQUENCY DISCRIMINATOR BLOCK DIAGRAM
+
HSP50214A
相關PDF資料
PDF描述
HSP50214B Programmable Downconverter
HSP50214BVC Programmable Downconverter
HSP50214BVI Programmable Downconverter
HT84 ADSL Coupling Transformers
HT84-00594 ADSL Coupling Transformers
相關代理商/技術參數(shù)
參數(shù)描述
HSP50214B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214B_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Downconverter
HSP50214BVC 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVCZ 功能描述:上下轉(zhuǎn)換器 120L MQFP COMTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214BVI 功能描述:上下轉(zhuǎn)換器 120L MQFP INDTEMP 14-BIT PROGRAMMABLE DOWNCONVERTER 65MSPS RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128
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