參數(shù)資料
型號(hào): HN58S65AI
廠商: Hitachi,Ltd.
英文描述: 8192-word ×8-bit Electrically Erasable and Programmable CMOS ROM(8k字×8位 EEPROM)
中文描述: 8192字× 8位電可擦除和可編程的CMOS光盤(8K的字× 8位的EEPROM)
文件頁(yè)數(shù): 14/19頁(yè)
文件大小: 134K
代理商: HN58S65AI
Datasheet Title
14
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30
μ
s from the preceding falling edge of
WE
or
CE
. When
CE
or
WE
is kept high for 100
μ
s after data input, the EEPROM enters write mode automatically and the
input data are written into the EEPROM.
Data
Polling
Data
polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
RDY/
Busy
Signal
RDY/
B us y
signal also allows status of the EEPROM to be determined. The RDY/
Busy
signal has high
impedance except in write cycle and is lowered to V
OL
after the first write signal. At the end of a write
cycle, the RDY/
Busy
signal changes state to high impedance.
WE
,
CE
Pin Operation
During a write cycle, addresses are latched by the falling edge of
WE
or
CE
, and data is latched by the
rising edge of
WE
or
CE
.
Write/Erase Endurance and Data Retention Time
The endurance is 10
5
cycles in case of the page programming and 10
4
cycles in case of the byte
programming (1% cumulative failure rate). The data retention time is more than 10 years when a device is
page-programmed less than 10
4
cycles.
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